Lines Matching +full:div +full:- +full:p

2 # SPDX-License-Identifier: Apache-2.0
14     f(PLL_P) = f(VCO clock) / PLLP  --> to I2S
15     f(PLL_Q) = f(VCO clock) / PLLQ  --> to RNG
16     f(PLL_R) = f(VCO clock) / PLLR  --> PLLCLK (System Clock)
22 compatible: "st,stm32g0-pll-clock"
24 include: [clock-controller.yaml, base.yaml]
27   "#clock-cells":
33   div-m:
38         Valid range: 1 - 8
40   mul-n:
45         Valid range: 8 - 86
47   div-p:
50         PLL division factor for PLL P output
51         Valid range: 2 - 32
53   div-q:
57         Valid range: 2 - 8
59   div-r:
64         Valid range: 2 - 8