Lines Matching +full:stm32 +full:- +full:window +full:- +full:watchdog
6 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/clock/stm32wb_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/adc/adc.h>
15 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
16 #include <zephyr/dt-bindings/dma/stm32_dma.h>
17 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
18 #include <zephyr/dt-bindings/reset/stm32wb_l_reset.h>
19 #include <zephyr/dt-bindings/power/stm32_pwr.h>
25 zephyr,flash-controller = &flash;
26 zephyr,bt-hci = &ble_rf;
30 #address-cells = <1>;
31 #size-cells = <0>;
35 compatible = "arm,cortex-m4f";
37 cpu-power-states = <&stop0 &stop1 &stop2>;
40 power-states {
42 compatible = "zephyr,power-state";
43 power-state-name = "suspend-to-idle";
44 substate-id = <1>;
45 min-residency-us = <100>;
48 compatible = "zephyr,power-state";
49 power-state-name = "suspend-to-idle";
50 substate-id = <2>;
51 min-residency-us = <500>;
54 compatible = "zephyr,power-state";
55 power-state-name = "suspend-to-idle";
56 substate-id = <3>;
57 min-residency-us = <900>;
63 compatible = "mmio-sram";
67 compatible = "zephyr,memory-region", "mmio-sram";
69 zephyr,memory-region = "SRAM1";
73 compatible = "zephyr,memory-region", "mmio-sram";
75 zephyr,memory-region = "SRAM2";
79 clk_hse: clk-hse {
80 #clock-cells = <0>;
81 compatible = "fixed-clock";
82 /* Expected clock-frequency on the whole series 32MHz */
83 clock-frequency = <DT_FREQ_M(32)>;
87 clk_hsi: clk-hsi {
88 #clock-cells = <0>;
89 compatible = "fixed-clock";
90 clock-frequency = <DT_FREQ_M(16)>;
94 clk_hsi48: clk-hsi48 {
95 #clock-cells = <0>;
96 compatible = "fixed-clock";
97 clock-frequency = <DT_FREQ_M(48)>;
101 clk_msi: clk-msi {
102 #clock-cells = <0>;
103 compatible = "st,stm32-msi-clock";
104 msi-range = <6>; /* 4MHz (reset value) */
108 clk_lse: clk-lse {
109 #clock-cells = <0>;
110 compatible = "st,stm32-lse-clock";
111 clock-frequency = <32768>;
112 driving-capability = <0>;
116 clk_lsi1: clk-lsi1 {
117 #clock-cells = <0>;
118 compatible = "fixed-clock";
119 clock-frequency = <DT_FREQ_K(32)>;
123 clk_lsi2: clk-lsi2 {
124 #clock-cells = <0>;
125 compatible = "fixed-clock";
126 clock-frequency = <DT_FREQ_K(32)>;
131 #clock-cells = <0>;
132 compatible = "st,stm32wb-pll-clock";
137 #clock-cells = <0>;
138 compatible = "st,stm32-clock-mux";
144 flash: flash-controller@58004000 {
145 compatible = "st,stm32-flash-controller", "st,stm32wb-flash-controller";
150 #address-cells = <1>;
151 #size-cells = <1>;
154 compatible = "st,stm32-nv-flash", "soc-nv-flash";
156 write-block-size = <8>;
157 erase-block-size = <4096>;
159 max-erase-time = <25>;
164 compatible = "st,stm32wb-rcc";
165 #clock-cells = <2>;
168 rctl: reset-controller {
169 compatible = "st,stm32-rcc-rctl";
170 #reset-cells = <1>;
174 exti: interrupt-controller@58000800 {
175 compatible = "st,stm32-exti";
176 interrupt-controller;
177 #interrupt-cells = <1>;
178 #address-cells = <1>;
180 num-lines = <16>;
183 interrupt-names = "line0", "line1", "line2", "line3",
184 "line4", "line5-9", "line10-15";
185 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
189 pinctrl: pin-controller@48000000 {
190 compatible = "st,stm32-pinctrl";
191 #address-cells = <1>;
192 #size-cells = <1>;
196 compatible = "st,stm32-gpio";
197 gpio-controller;
198 #gpio-cells = <2>;
204 compatible = "st,stm32-gpio";
205 gpio-controller;
206 #gpio-cells = <2>;
212 compatible = "st,stm32-gpio";
213 gpio-controller;
214 #gpio-cells = <2>;
220 compatible = "st,stm32-gpio";
221 gpio-controller;
222 #gpio-cells = <2>;
228 compatible = "st,stm32-gpio";
229 gpio-controller;
230 #gpio-cells = <2>;
237 compatible = "st,stm32-gpio";
238 gpio-controller;
239 #gpio-cells = <2>;
246 wwdg: watchdog@40002c00 {
247 compatible = "st,stm32-window-watchdog";
255 compatible = "st,stm32-usart", "st,stm32-uart";
264 compatible = "st,stm32-i2c-v2";
265 clock-frequency = <I2C_BITRATE_STANDARD>;
266 #address-cells = <1>;
267 #size-cells = <0>;
271 interrupt-names = "event", "error";
276 compatible = "st,stm32-i2c-v2";
277 clock-frequency = <I2C_BITRATE_STANDARD>;
278 #address-cells = <1>;
279 #size-cells = <0>;
283 interrupt-names = "event", "error";
288 compatible = "st,stm32-rtc";
293 alarms-count = <2>;
294 alrm-exti-line = <17>;
298 compatible = "st,stm32-bbram";
299 st,backup-regs = <20>;
305 compatible = "st,stm32-spi-fifo", "st,stm32-spi";
306 #address-cells = <1>;
307 #size-cells = <0>;
315 compatible = "st,stm32-spi-fifo", "st,stm32-spi";
316 #address-cells = <1>;
317 #size-cells = <0>;
325 compatible = "st,stm32-lpuart", "st,stm32-uart";
334 compatible = "st,stm32-timers";
339 interrupt-names = "brk", "up", "trgcom", "cc";
344 compatible = "st,stm32-pwm";
346 #pwm-cells = <3>;
351 compatible = "st,stm32-timers";
356 interrupt-names = "global";
361 compatible = "st,stm32-pwm";
363 #pwm-cells = <3>;
367 compatible = "st,stm32-counter";
373 compatible = "st,stm32-timers";
378 interrupt-names = "global";
383 compatible = "st,stm32-pwm";
385 #pwm-cells = <3>;
389 compatible = "st,stm32-counter";
395 compatible = "st,stm32-timers";
400 interrupt-names = "global";
405 compatible = "st,stm32-pwm";
407 #pwm-cells = <3>;
411 compatible = "st,stm32-counter";
417 compatible = "st,stm32-adc";
422 #io-channel-cells = <1>;
427 sampling-times = <3 7 13 25 48 93 248 641>;
428 st,adc-sequencer = "FULLY_CONFIGURABLE";
429 st,adc-oversampler = "OVERSAMPLER_MINIMAL";
432 iwdg: watchdog@40003000 {
433 compatible = "st,stm32-watchdog";
439 compatible = "st,stm32-lptim";
441 #address-cells = <1>;
442 #size-cells = <0>;
445 interrupt-names = "wakeup";
450 compatible = "st,stm32-dma-v2";
451 #dma-cells = <3>;
455 dma-requests = <7>;
456 dma-offset = <0>;
461 compatible = "st,stm32-dma-v2";
462 #dma-cells = <3>;
466 dma-requests = <7>;
467 dma-offset = <7>;
472 compatible = "st,stm32-dmamux";
473 #dma-cells = <3>;
477 dma-channels = <14>;
478 dma-generators = <4>;
479 dma-requests= <36>;
484 compatible = "st,stm32-usb";
487 interrupt-names = "usb", "usbhp";
488 num-bidir-endpoints = <8>;
489 ram-size = <1024>;
497 compatible = "st,stm32-qspi";
498 #address-cells = <0x1>;
499 #size-cells = <0x0>;
507 compatible = "st,stm32-rng";
515 compatible = "st,stm32-aes";
524 compatible = "st,stm32-pwr";
528 wkup-pins-nb = <5>; /* 5 system wake-up pins */
529 wkup-pins-pol;
530 wkup-pins-pupd;
532 #address-cells = <1>;
533 #size-cells = <0>;
535 wkup-pin@1 {
537 wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_SRC_0>;
540 wkup-pin@4 {
542 wkup-gpios = <&gpioa 2 STM32_PWR_WKUP_PIN_SRC_0>;
548 compatible = "st,stm32-temp-cal";
549 ts-cal1-addr = <0x1FFF75A8>;
550 ts-cal2-addr = <0x1FFF75CA>;
551 ts-cal1-temp = <30>;
552 ts-cal2-temp = <130>;
553 ts-cal-vrefanalog = <3000>;
554 io-channels = <&adc1 17>;
559 compatible = "st,stm32-vref";
560 vrefint-cal-addr = <0x1FFF75AA>;
561 vrefint-cal-mv = <3600>;
562 io-channels = <&adc1 0>;
567 compatible = "st,stm32-vbat";
569 io-channels = <&adc1 18>;
574 compatible = "usb-nop-xceiv";
575 #phy-cells = <0>;
579 compatible = "st,stm32wb-rf";
585 compatible = "st,stm32-smbus";
586 #address-cells = <1>;
587 #size-cells = <0>;
593 compatible = "st,stm32-smbus";
594 #address-cells = <1>;
595 #size-cells = <0>;
602 arm,num-irq-priority-bits = <4>;