Lines Matching +full:stm32 +full:- +full:fdcan
7 * SPDX-License-Identifier: Apache-2.0
11 #include <arm/armv8-m.dtsi>
12 #include <zephyr/dt-bindings/adc/adc.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/clock/stm32u5_clock.h>
15 #include <zephyr/dt-bindings/gpio/gpio.h>
16 #include <zephyr/dt-bindings/i2c/i2c.h>
17 #include <zephyr/dt-bindings/flash_controller/ospi.h>
18 #include <zephyr/dt-bindings/reset/stm32u5_reset.h>
19 #include <zephyr/dt-bindings/dma/stm32_dma.h>
20 #include <zephyr/dt-bindings/memory-controller/stm32-fmc-nor-psram.h>
21 #include <zephyr/dt-bindings/adc/stm32u5_adc.h>
22 #include <zephyr/dt-bindings/power/stm32_pwr.h>
28 zephyr,flash-controller = &flash;
32 #address-cells = <1>;
33 #size-cells = <0>;
37 compatible = "arm,cortex-m33";
39 #address-cells = <1>;
40 #size-cells = <1>;
41 cpu-power-states = <&stop0 &stop1 &stop2>;
44 compatible = "arm,armv8m-mpu";
49 power-states {
51 compatible = "zephyr,power-state";
52 power-state-name = "suspend-to-idle";
53 substate-id = <1>;
54 min-residency-us = <100>;
57 compatible = "zephyr,power-state";
58 power-state-name = "suspend-to-idle";
59 substate-id = <2>;
60 min-residency-us = <500>;
63 compatible = "zephyr,power-state";
64 power-state-name = "suspend-to-idle";
65 substate-id = <3>;
66 min-residency-us = <900>;
68 /omit-if-no-ref/ stop3: state3 {
69 compatible = "zephyr,power-state";
70 power-state-name = "suspend-to-idle";
71 substate-id = <4>;
72 min-residency-us = <200000>;
73 exit-latency-us = <130>;
79 compatible = "mmio-sram";
83 clk_hse: clk-hse {
84 #clock-cells = <0>;
85 compatible = "st,stm32-hse-clock";
89 clk_hsi: clk-hsi {
90 #clock-cells = <0>;
91 compatible = "fixed-clock";
92 clock-frequency = <DT_FREQ_M(16)>;
96 clk_hsi48: clk-hsi48 {
97 #clock-cells = <0>;
98 compatible = "fixed-clock";
99 clock-frequency = <DT_FREQ_M(48)>;
103 clk_msis: clk-msis {
104 #clock-cells = <0>;
105 compatible = "st,stm32u5-msi-clock";
106 msi-range = <4>; /* 4MHz (reset value) */
110 clk_msik: clk-msik {
111 #clock-cells = <0>;
112 compatible = "st,stm32u5-msi-clock";
113 msi-range = <4>; /* 4MHz (reset value) */
117 clk_lse: clk-lse {
118 #clock-cells = <0>;
119 compatible = "st,stm32-lse-clock";
120 clock-frequency = <32768>;
121 driving-capability = <2>;
125 clk_lsi: clk-lsi {
126 #clock-cells = <0>;
127 compatible = "fixed-clock";
128 clock-frequency = <DT_FREQ_K(32)>;
133 #clock-cells = <0>;
134 compatible = "st,stm32u5-pll-clock";
139 #clock-cells = <0>;
140 compatible = "st,stm32u5-pll-clock";
145 #clock-cells = <0>;
146 compatible = "st,stm32u5-pll-clock";
153 compatible = "st,stm32-clock-mco";
159 flash: flash-controller@40022000 {
160 compatible = "st,stm32-flash-controller", "st,stm32l5-flash-controller";
164 #address-cells = <1>;
165 #size-cells = <1>;
168 compatible = "st,stm32-nv-flash", "soc-nv-flash";
170 write-block-size = <16>;
171 erase-block-size = <8192>;
173 max-erase-time = <5>;
178 compatible = "st,stm32u5-rcc";
179 clocks-controller;
180 #clock-cells = <2>;
183 rctl: reset-controller {
184 compatible = "st,stm32-rcc-rctl";
185 #reset-cells = <1>;
189 exti: interrupt-controller@46022000 {
190 compatible = "st,stm32g0-exti", "st,stm32-exti";
191 interrupt-controller;
192 #interrupt-cells = <1>;
193 #address-cells = <1>;
195 num-lines = <16>;
200 interrupt-names = "line0", "line1", "line2", "line3",
204 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
210 pinctrl: pin-controller@42020000 {
211 compatible = "st,stm32-pinctrl";
212 #address-cells = <1>;
213 #size-cells = <1>;
217 compatible = "st,stm32-gpio";
218 gpio-controller;
219 #gpio-cells = <2>;
225 compatible = "st,stm32-gpio";
226 gpio-controller;
227 #gpio-cells = <2>;
233 compatible = "st,stm32-gpio";
234 gpio-controller;
235 #gpio-cells = <2>;
241 compatible = "st,stm32-gpio";
242 gpio-controller;
243 #gpio-cells = <2>;
249 compatible = "st,stm32-gpio";
250 gpio-controller;
251 #gpio-cells = <2>;
257 compatible = "st,stm32-gpio";
258 gpio-controller;
259 #gpio-cells = <2>;
265 compatible = "st,stm32-gpio";
266 gpio-controller;
267 #gpio-cells = <2>;
273 compatible = "st,stm32-gpio";
274 gpio-controller;
275 #gpio-cells = <2>;
281 compatible = "st,stm32-gpio";
282 gpio-controller;
283 #gpio-cells = <2>;
290 compatible = "st,stm32-watchdog";
296 compatible = "st,stm32-window-watchdog";
304 compatible = "zephyr,memory-region", "st,stm32-backup-sram";
308 zephyr,memory-region = "BACKUP_SRAM";
313 compatible = "st,stm32-usart", "st,stm32-uart";
322 compatible = "st,stm32-usart", "st,stm32-uart";
331 compatible = "st,stm32-usart", "st,stm32-uart";
340 compatible = "st,stm32-uart";
349 compatible = "st,stm32-uart";
358 compatible = "st,stm32-lpuart", "st,stm32-uart";
367 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
368 #address-cells = <1>;
369 #size-cells = <0>;
377 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
378 #address-cells = <1>;
379 #size-cells = <0>;
387 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
388 #address-cells = <1>;
389 #size-cells = <0>;
397 compatible = "st,stm32-i2c-v2";
398 clock-frequency = <I2C_BITRATE_STANDARD>;
399 #address-cells = <1>;
400 #size-cells = <0>;
404 interrupt-names = "event", "error";
409 compatible = "st,stm32-i2c-v2";
410 clock-frequency = <I2C_BITRATE_STANDARD>;
411 #address-cells = <1>;
412 #size-cells = <0>;
416 interrupt-names = "event", "error";
421 compatible = "st,stm32-i2c-v2";
422 clock-frequency = <I2C_BITRATE_STANDARD>;
423 #address-cells = <1>;
424 #size-cells = <0>;
428 interrupt-names = "event", "error";
433 compatible = "st,stm32-i2c-v2";
434 clock-frequency = <I2C_BITRATE_STANDARD>;
435 #address-cells = <1>;
436 #size-cells = <0>;
440 interrupt-names = "event", "error";
445 compatible = "st,stm32-lptim";
446 #address-cells = <1>;
447 #size-cells = <0>;
451 interrupt-names = "wakeup";
456 compatible = "st,stm32-lptim";
457 #address-cells = <1>;
458 #size-cells = <0>;
462 interrupt-names = "global";
467 compatible = "st,stm32-lptim";
468 #address-cells = <1>;
469 #size-cells = <0>;
473 interrupt-names = "global";
478 compatible = "st,stm32-lptim";
479 #address-cells = <1>;
480 #size-cells = <0>;
484 interrupt-names = "global";
489 compatible = "st,stm32-rtc";
494 alarms-count = <2>;
499 compatible = "st,stm32-timers";
504 interrupt-names = "brk", "up", "trgcom", "cc";
508 compatible = "st,stm32-pwm";
510 #pwm-cells = <3>;
515 compatible = "st,stm32-timers";
520 interrupt-names = "global";
524 compatible = "st,stm32-pwm";
526 #pwm-cells = <3>;
531 compatible = "st,stm32-timers";
536 interrupt-names = "global";
540 compatible = "st,stm32-pwm";
542 #pwm-cells = <3>;
547 compatible = "st,stm32-timers";
552 interrupt-names = "global";
556 compatible = "st,stm32-pwm";
558 #pwm-cells = <3>;
562 compatible = "st,stm32-counter";
568 compatible = "st,stm32-timers";
573 interrupt-names = "global";
577 compatible = "st,stm32-pwm";
579 #pwm-cells = <3>;
583 compatible = "st,stm32-counter";
589 compatible = "st,stm32-timers";
594 interrupt-names = "global";
598 compatible = "st,stm32-pwm";
600 #pwm-cells = <3>;
605 compatible = "st,stm32-timers";
610 interrupt-names = "global";
614 compatible = "st,stm32-pwm";
616 #pwm-cells = <3>;
621 compatible = "st,stm32-timers";
626 interrupt-names = "brk", "up", "trgcom", "cc";
630 compatible = "st,stm32-pwm";
632 #pwm-cells = <3>;
637 compatible = "st,stm32-timers";
642 interrupt-names = "global";
646 compatible = "st,stm32-pwm";
648 #pwm-cells = <3>;
652 compatible = "st,stm32-counter";
658 compatible = "st,stm32-timers";
663 interrupt-names = "global";
667 compatible = "st,stm32-pwm";
669 #pwm-cells = <3>;
673 compatible = "st,stm32-counter";
679 compatible = "st,stm32-timers";
684 interrupt-names = "global";
688 compatible = "st,stm32-pwm";
690 #pwm-cells = <3>;
694 compatible = "st,stm32-counter";
700 compatible = "st,stm32-ospi";
703 clock-names = "ospix", "ospi-ker", "ospi-mgr";
707 #address-cells = <1>;
708 #size-cells = <0>;
713 compatible = "st,stm32-ospi";
716 clock-names = "ospix", "ospi-ker", "ospi-mgr";
720 #address-cells = <1>;
721 #size-cells = <0>;
726 compatible = "st,stm32-aes";
735 compatible = "st,stm32-rng";
739 nist-config = <0xf60d00>;
740 health-test-config = <0x9aae>;
754 compatible = "st,stm32-sdmmc";
764 compatible = "st,stm32-sdmmc";
774 compatible = "st,stm32-dac";
778 #io-channel-cells = <1>;
782 compatible = "st,stm32-adc";
788 #io-channel-cells = <1>;
793 sampling-times = <5 6 12 20 36 68 391 814>;
794 st,adc-clock-source = "ASYNC";
795 st,adc-sequencer = "FULLY_CONFIGURABLE";
796 st,adc-oversampler = "OVERSAMPLER_EXTENDED";
800 compatible = "st,stm32-adc";
806 #io-channel-cells = <1>;
811 sampling-times = <2 4 8 13 20 40 80 815>;
812 num-sampling-time-common-channels = <2>;
813 st,adc-clock-source = "ASYNC";
814 st,adc-sequencer = "NOT_FULLY_CONFIGURABLE";
815 st,adc-oversampler = "OVERSAMPLER_MINIMAL";
819 compatible = "st,stm32-fdcan";
821 reg-names = "m_can", "message_ram";
823 interrupt-names = "int0", "int1";
825 bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>;
830 compatible = "st,stm32-ucpd";
838 compatible = "st,stm32u5-dma";
839 #dma-cells = <3>;
844 dma-channels = <16>;
845 dma-requests = <114>;
846 dma-offset = <0>;
850 fmc: memory-controller@420d0400 {
851 compatible = "st,stm32-fmc";
857 compatible = "st,stm32-fmc-nor-psram";
858 #address-cells = <1>;
859 #size-cells = <0>;
865 compatible = "st,stm32-pwr";
869 wkup-pins-nb = <8>; /* 8 system wake-up pins */
870 wkup-pin-srcs = <3>; /* 3 gpio sources associated with each wkup pin */
871 wkup-pins-pol;
872 wkup-pins-pupd;
874 #address-cells = <1>;
875 #size-cells = <0>;
877 wkup-pin@1 {
879 wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_SRC_0>,
884 wkup-pin@2 {
886 wkup-gpios = <&gpioa 4 STM32_PWR_WKUP_PIN_SRC_0>,
891 wkup-pin@3 {
893 wkup-gpios = <&gpioe 6 STM32_PWR_WKUP_PIN_SRC_0>,
898 wkup-pin@4 {
900 wkup-gpios = <&gpioa 2 STM32_PWR_WKUP_PIN_SRC_0>,
905 wkup-pin@5 {
907 wkup-gpios = <&gpioc 5 STM32_PWR_WKUP_PIN_SRC_0>,
912 wkup-pin@6 {
914 wkup-gpios = <&gpiob 5 STM32_PWR_WKUP_PIN_SRC_0>,
919 wkup-pin@7 {
921 wkup-gpios = <&gpiob 15 STM32_PWR_WKUP_PIN_SRC_0>,
926 wkup-pin@8 {
928 wkup-gpios = <&gpiof 2 STM32_PWR_WKUP_PIN_SRC_0>,
937 compatible = "swj-connector";
938 pinctrl-0 = <&debug_jtms_swdio_pa13 &debug_jtck_swclk_pa14
941 pinctrl-1 = <&analog_pa13 &analog_pa14 &analog_pa15
943 pinctrl-names = "default", "sleep";
947 compatible = "st,stm32-temp-cal";
948 ts-cal1-addr = <0x0BFA0710>;
949 ts-cal2-addr = <0x0BFA0742>;
950 ts-cal1-temp = <30>;
951 ts-cal2-temp = <130>;
952 ts-cal-vrefanalog = <3000>;
953 ts-cal-resolution = <14>;
954 io-channels = <&adc1 19>;
959 compatible = "st,stm32-vref";
960 vrefint-cal-addr = <0x0BFA07A5>;
961 vrefint-cal-mv = <3000>;
962 io-channels = <&adc1 0>;
967 compatible = "st,stm32-vref";
968 vrefint-cal-addr = <0x0BFA07A5>;
969 vrefint-cal-mv = <3000>;
970 io-channels = <&adc4 0>;
975 compatible = "st,stm32-vbat";
977 io-channels = <&adc1 18>;
982 compatible = "st,stm32-vbat";
984 io-channels = <&adc4 14>;
989 compatible = "st,stm32-smbus";
990 #address-cells = <1>;
991 #size-cells = <0>;
997 compatible = "st,stm32-smbus";
998 #address-cells = <1>;
999 #size-cells = <0>;
1005 compatible = "st,stm32-smbus";
1006 #address-cells = <1>;
1007 #size-cells = <0>;
1013 compatible = "st,stm32-smbus";
1014 #address-cells = <1>;
1015 #size-cells = <0>;
1022 arm,num-irq-priority-bits = <4>;