Lines Matching +full:1 +full:st
32 #address-cells = <1>;
39 #address-cells = <1>;
40 #size-cells = <1>;
53 substate-id = <1>;
85 compatible = "st,stm32-hse-clock";
105 compatible = "st,stm32u5-msi-clock";
112 compatible = "st,stm32u5-msi-clock";
119 compatible = "st,stm32-lse-clock";
134 compatible = "st,stm32u5-pll-clock";
140 compatible = "st,stm32u5-pll-clock";
146 compatible = "st,stm32u5-pll-clock";
153 compatible = "st,stm32-clock-mco";
160 compatible = "st,stm32-flash-controller", "st,stm32l5-flash-controller";
164 #address-cells = <1>;
165 #size-cells = <1>;
168 compatible = "st,stm32-nv-flash", "soc-nv-flash";
178 compatible = "st,stm32u5-rcc";
184 compatible = "st,stm32-rcc-rctl";
185 #reset-cells = <1>;
190 compatible = "st,stm32g0-exti", "st,stm32-exti";
192 #interrupt-cells = <1>;
193 #address-cells = <1>;
204 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
205 <4 1>, <5 1>, <6 1>, <7 1>,
206 <8 1>, <9 1>, <10 1>, <11 1>,
207 <12 1>, <13 1>, <14 1>, <15 1>;
211 compatible = "st,stm32-pinctrl";
212 #address-cells = <1>;
213 #size-cells = <1>;
217 compatible = "st,stm32-gpio";
225 compatible = "st,stm32-gpio";
229 clocks = <&rcc STM32_CLOCK(AHB2, 1U)>;
233 compatible = "st,stm32-gpio";
241 compatible = "st,stm32-gpio";
249 compatible = "st,stm32-gpio";
257 compatible = "st,stm32-gpio";
265 compatible = "st,stm32-gpio";
273 compatible = "st,stm32-gpio";
281 compatible = "st,stm32-gpio";
290 compatible = "st,stm32-watchdog";
296 compatible = "st,stm32-window-watchdog";
304 compatible = "zephyr,memory-region", "st,stm32-backup-sram";
313 compatible = "st,stm32-usart", "st,stm32-uart";
322 compatible = "st,stm32-usart", "st,stm32-uart";
331 compatible = "st,stm32-usart", "st,stm32-uart";
340 compatible = "st,stm32-uart";
349 compatible = "st,stm32-uart";
358 compatible = "st,stm32-lpuart", "st,stm32-uart";
367 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
368 #address-cells = <1>;
377 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
378 #address-cells = <1>;
387 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
388 #address-cells = <1>;
397 compatible = "st,stm32-i2c-v2";
399 #address-cells = <1>;
409 compatible = "st,stm32-i2c-v2";
411 #address-cells = <1>;
421 compatible = "st,stm32-i2c-v2";
423 #address-cells = <1>;
433 compatible = "st,stm32-i2c-v2";
435 #address-cells = <1>;
438 clocks = <&rcc STM32_CLOCK(APB1_2, 1U)>;
445 compatible = "st,stm32-lptim";
446 #address-cells = <1>;
450 interrupts = <67 1>;
456 compatible = "st,stm32-lptim";
457 #address-cells = <1>;
467 compatible = "st,stm32-lptim";
468 #address-cells = <1>;
478 compatible = "st,stm32-lptim";
479 #address-cells = <1>;
489 compatible = "st,stm32-rtc";
499 compatible = "st,stm32-timers";
508 compatible = "st,stm32-pwm";
515 compatible = "st,stm32-timers";
524 compatible = "st,stm32-pwm";
531 compatible = "st,stm32-timers";
533 clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
534 resets = <&rctl STM32_RESET(APB1L, 1U)>;
540 compatible = "st,stm32-pwm";
547 compatible = "st,stm32-timers";
556 compatible = "st,stm32-pwm";
562 compatible = "st,stm32-counter";
568 compatible = "st,stm32-timers";
577 compatible = "st,stm32-pwm";
583 compatible = "st,stm32-counter";
589 compatible = "st,stm32-timers";
598 compatible = "st,stm32-pwm";
605 compatible = "st,stm32-timers";
614 compatible = "st,stm32-pwm";
621 compatible = "st,stm32-timers";
630 compatible = "st,stm32-pwm";
637 compatible = "st,stm32-timers";
646 compatible = "st,stm32-pwm";
652 compatible = "st,stm32-counter";
658 compatible = "st,stm32-timers";
667 compatible = "st,stm32-pwm";
673 compatible = "st,stm32-counter";
679 compatible = "st,stm32-timers";
688 compatible = "st,stm32-pwm";
694 compatible = "st,stm32-counter";
700 compatible = "st,stm32-ospi";
707 #address-cells = <1>;
713 compatible = "st,stm32-ospi";
720 #address-cells = <1>;
726 compatible = "st,stm32-aes";
735 compatible = "st,stm32-rng";
754 compatible = "st,stm32-sdmmc";
764 compatible = "st,stm32-sdmmc";
774 compatible = "st,stm32-dac";
778 #io-channel-cells = <1>;
782 compatible = "st,stm32-adc";
788 #io-channel-cells = <1>;
794 st,adc-clock-source = "ASYNC";
795 st,adc-sequencer = "FULLY_CONFIGURABLE";
796 st,adc-oversampler = "OVERSAMPLER_EXTENDED";
800 compatible = "st,stm32-adc";
806 #io-channel-cells = <1>;
813 st,adc-clock-source = "ASYNC";
814 st,adc-sequencer = "NOT_FULLY_CONFIGURABLE";
815 st,adc-oversampler = "OVERSAMPLER_MINIMAL";
819 compatible = "st,stm32-fdcan";
830 compatible = "st,stm32-ucpd";
838 compatible = "st,stm32u5-dma";
851 compatible = "st,stm32-fmc";
857 compatible = "st,stm32-fmc-nor-psram";
858 #address-cells = <1>;
865 compatible = "st,stm32-pwr";
874 #address-cells = <1>;
877 wkup-pin@1 {
894 <&gpioa 1 STM32_PWR_WKUP_PIN_SRC_1>,
901 <&gpiob 1 STM32_PWR_WKUP_PIN_SRC_1>,
941 pinctrl-1 = <&analog_pa13 &analog_pa14 &analog_pa15
947 compatible = "st,stm32-temp-cal";
959 compatible = "st,stm32-vref";
967 compatible = "st,stm32-vref";
975 compatible = "st,stm32-vbat";
982 compatible = "st,stm32-vbat";
989 compatible = "st,stm32-smbus";
990 #address-cells = <1>;
997 compatible = "st,stm32-smbus";
998 #address-cells = <1>;
1005 compatible = "st,stm32-smbus";
1006 #address-cells = <1>;
1013 compatible = "st,stm32-smbus";
1014 #address-cells = <1>;