Lines Matching +full:stm32 +full:- +full:rcc
4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32l471", "st,stm32l4", "simple-bus";
13 pinctrl: pin-controller@48000000 {
16 compatible = "st,stm32-gpio";
17 gpio-controller;
18 #gpio-cells = <2>;
20 clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
24 compatible = "st,stm32-gpio";
25 gpio-controller;
26 #gpio-cells = <2>;
28 clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
32 compatible = "st,stm32-gpio";
33 gpio-controller;
34 #gpio-cells = <2>;
36 clocks = <&rcc STM32_CLOCK(AHB2, 5U)>;
40 compatible = "st,stm32-gpio";
41 gpio-controller;
42 #gpio-cells = <2>;
44 clocks = <&rcc STM32_CLOCK(AHB2, 6U)>;
49 compatible = "st,stm32-usart", "st,stm32-uart";
51 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
58 compatible = "st,stm32-uart";
60 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
67 compatible = "st,stm32-uart";
69 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
76 compatible = "st,stm32-i2c-v2";
77 clock-frequency = <I2C_BITRATE_STANDARD>;
78 #address-cells = <1>;
79 #size-cells = <0>;
81 clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
83 interrupt-names = "event", "error";
88 compatible = "st,stm32-spi-fifo", "st,stm32-spi";
89 #address-cells = <1>;
90 #size-cells = <0>;
92 clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
98 compatible = "st,stm32-spi-fifo", "st,stm32-spi";
99 #address-cells = <1>;
100 #size-cells = <0>;
102 clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
108 compatible = "st,stm32-timers";
110 clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
113 interrupt-names = "global";
118 compatible = "st,stm32-pwm";
120 #pwm-cells = <3>;
124 compatible = "st,stm32-counter";
130 compatible = "st,stm32-timers";
132 clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
135 interrupt-names = "global";
140 compatible = "st,stm32-pwm";
142 #pwm-cells = <3>;
146 compatible = "st,stm32-counter";
152 compatible = "st,stm32-timers";
154 clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
157 interrupt-names = "global";
162 compatible = "st,stm32-pwm";
164 #pwm-cells = <3>;
168 compatible = "st,stm32-counter";
174 compatible = "st,stm32-timers";
176 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
179 interrupt-names = "global";
184 compatible = "st,stm32-counter";
190 compatible = "st,stm32-timers";
192 clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
195 interrupt-names = "brk", "up", "trgcom", "cc";
200 compatible = "st,stm32-pwm";
202 #pwm-cells = <3>;
207 compatible = "st,stm32-timers";
209 clocks = <&rcc STM32_CLOCK(APB2, 18U)>;
212 interrupt-names = "global";
217 compatible = "st,stm32-pwm";
219 #pwm-cells = <3>;
223 compatible = "st,stm32-counter";
229 compatible = "st,stm32-bxcan";
232 interrupt-names = "TX", "RX0", "RX1", "SCE";
233 clocks = <&rcc STM32_CLOCK(APB1, 25U)>; //RCC_APB1ENR1_CAN1EN
238 compatible = "st,stm32-sdmmc";
240 clocks = <&rcc STM32_CLOCK(APB2, 10U)>,
241 <&rcc STM32_SRC_MSI CLK48_SEL(3)>;
248 compatible = "st,stm32-dac";
250 clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
252 #io-channel-cells = <1>;
256 compatible = "st,stm32-adc";
258 clocks = <&rcc STM32_CLOCK(AHB2, 13U)>;
261 #io-channel-cells = <1>;
266 compatible = "st,stm32-bbram";
267 st,backup-regs = <32>;
274 ts-cal2-temp = <110>;
278 compatible = "st,stm32-smbus";
279 #address-cells = <1>;
280 #size-cells = <0>;