Lines Matching +full:stm32 +full:- +full:rcc
4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/flash_controller/ospi.h>
10 #include <zephyr/dt-bindings/flash_controller/xspi.h>
17 #clock-cells = <0>;
18 compatible = "st,stm32u5-pll-clock";
24 compatible = "st,stm32h562", "st,stm32h5", "simple-bus";
26 pinctrl: pin-controller@42020000 {
28 compatible = "st,stm32-gpio";
29 gpio-controller;
30 #gpio-cells = <2>;
32 clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
36 compatible = "st,stm32-gpio";
37 gpio-controller;
38 #gpio-cells = <2>;
40 clocks = <&rcc STM32_CLOCK(AHB2, 5U)>;
44 compatible = "st,stm32-gpio";
45 gpio-controller;
46 #gpio-cells = <2>;
48 clocks = <&rcc STM32_CLOCK(AHB2, 6U)>;
52 compatible = "st,stm32-gpio";
53 gpio-controller;
54 #gpio-cells = <2>;
56 clocks = <&rcc STM32_CLOCK(AHB2, 8U)>;
61 compatible = "zephyr,memory-region", "mmio-sram";
63 zephyr,memory-region = "SRAM1";
67 compatible = "zephyr,memory-region", "mmio-sram";
69 zephyr,memory-region = "SRAM2";
73 compatible = "zephyr,memory-region", "mmio-sram";
75 zephyr,memory-region = "SRAM3";
83 compatible = "st,stm32-lptim";
84 clocks = <&rcc STM32_CLOCK(APB3, 12U)>;
85 #address-cells = <1>;
86 #size-cells = <0>;
89 interrupt-names = "wakeup";
94 compatible = "st,stm32-lptim";
95 clocks = <&rcc STM32_CLOCK(APB3, 13U)>;
96 #address-cells = <1>;
97 #size-cells = <0>;
100 interrupt-names = "wakeup";
105 compatible = "st,stm32-lptim";
106 clocks = <&rcc STM32_CLOCK(APB3, 14U)>;
107 #address-cells = <1>;
108 #size-cells = <0>;
111 interrupt-names = "wakeup";
116 compatible = "st,stm32-lptim";
117 clocks = <&rcc STM32_CLOCK(APB3, 15U)>;
118 #address-cells = <1>;
119 #size-cells = <0>;
122 interrupt-names = "wakeup";
127 compatible = "st,stm32-uart";
129 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
136 compatible = "st,stm32-uart";
138 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
145 compatible = "st,stm32-uart";
147 clocks = <&rcc STM32_CLOCK(APB1, 30U)>;
154 compatible = "st,stm32-uart";
156 clocks = <&rcc STM32_CLOCK(APB1, 31U)>;
163 compatible = "st,stm32-uart";
165 clocks = <&rcc STM32_CLOCK(APB1_2, 0U)>;
172 compatible = "st,stm32-usart", "st,stm32-uart";
174 clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
181 compatible = "st,stm32-usart", "st,stm32-uart";
183 clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
190 compatible = "st,stm32-usart", "st,stm32-uart";
192 clocks = <&rcc STM32_CLOCK(APB1, 27U)>;
199 compatible = "st,stm32-uart";
201 clocks = <&rcc STM32_CLOCK(APB1_2, 1U)>;
208 compatible = "st,stm32-i2c-v2";
209 clock-frequency = <I2C_BITRATE_STANDARD>;
210 #address-cells = <1>;
211 #size-cells = <0>;
213 clocks = <&rcc STM32_CLOCK(APB3, 7U)>;
215 interrupt-names = "event", "error";
220 compatible = "st,stm32-i2c-v2";
221 clock-frequency = <I2C_BITRATE_STANDARD>;
222 #address-cells = <1>;
223 #size-cells = <0>;
225 clocks = <&rcc STM32_CLOCK(APB3, 8U)>;
227 interrupt-names = "event", "error";
232 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
233 #address-cells = <1>;
234 #size-cells = <0>;
237 clocks = <&rcc STM32_CLOCK(APB2, 19U)>;
242 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
243 #address-cells = <1>;
244 #size-cells = <0>;
247 clocks = <&rcc STM32_CLOCK(APB3, 5U)>;
252 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
253 #address-cells = <1>;
254 #size-cells = <0>;
257 clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
262 compatible = "st,stm32-xspi";
265 clock-names = "xspix", "xspi-ker";
266 clocks = <&rcc STM32_CLOCK(AHB4, 20U)>,
267 <&rcc STM32_SRC_PLL1_Q OCTOSPI1_SEL(1)>;
268 #address-cells = <1>;
269 #size-cells = <0>;
274 compatible = "st,stm32-adc";
276 clocks = <&rcc STM32_CLOCK(AHB2, 10U)>;
279 vref-mv = <3300>;
280 #io-channel-cells = <1>;
285 sampling-times = <3 7 13 25 48 93 248 641>;
286 st,adc-sequencer = "FULLY_CONFIGURABLE";
287 st,adc-oversampler = "OVERSAMPLER_MINIMAL";
291 compatible = "st,stm32-timers";
293 clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
296 interrupt-names = "global";
300 compatible = "st,stm32-pwm";
302 #pwm-cells = <3>;
306 compatible = "st,stm32-counter";
312 compatible = "st,stm32-timers";
314 clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
317 interrupt-names = "global";
321 compatible = "st,stm32-pwm";
323 #pwm-cells = <3>;
327 compatible = "st,stm32-counter";
333 compatible = "st,stm32-timers";
335 clocks = <&rcc STM32_CLOCK(APB1, 6U)>;
338 interrupt-names = "global";
342 compatible = "st,stm32-pwm";
344 #pwm-cells = <3>;
348 compatible = "st,stm32-counter";
354 compatible = "st,stm32-timers";
356 clocks = <&rcc STM32_CLOCK(APB1, 7U)>;
359 interrupt-names = "global";
363 compatible = "st,stm32-pwm";
365 #pwm-cells = <3>;
369 compatible = "st,stm32-counter";
375 compatible = "st,stm32-timers";
377 clocks = <&rcc STM32_CLOCK(APB1, 8U)>;
380 interrupt-names = "global";
384 compatible = "st,stm32-pwm";
386 #pwm-cells = <3>;
390 compatible = "st,stm32-counter";
396 compatible = "st,stm32-timers";
398 clocks = <&rcc STM32_CLOCK(APB2, 16U)>;
401 interrupt-names = "global";
405 compatible = "st,stm32-pwm";
407 #pwm-cells = <3>;
411 compatible = "st,stm32-counter";
417 compatible = "st,stm32-timers";
419 clocks = <&rcc STM32_CLOCK(APB2, 17U)>;
422 interrupt-names = "global";
426 compatible = "st,stm32-pwm";
428 #pwm-cells = <3>;
432 compatible = "st,stm32-counter";
438 compatible = "st,stm32-timers";
440 clocks = <&rcc STM32_CLOCK(APB2, 18U)>;
443 interrupt-names = "global";
447 compatible = "st,stm32-pwm";
449 #pwm-cells = <3>;
453 compatible = "st,stm32-counter";
459 compatible = "st,stm32-aes";
461 clocks = <&rcc STM32_CLOCK(AHB2, 16U)>;
468 compatible = "st,stm32-fdcan";
470 reg-names = "m_can", "message_ram";
472 interrupt-names = "int0", "int1";
474 clocks = <&rcc STM32_CLOCK(APB1_2, 9U)>;
475 bosch,mram-cfg = <0x350 28 8 3 3 0 3 3>;
480 compatible = "st,stm32-sdmmc";
482 clocks = <&rcc STM32_CLOCK(AHB4, 11U)>,
483 <&rcc STM32_SRC_PLL1_Q SDMMC1_SEL(0)>;
489 fmc: memory-controller@47000400 {
490 compatible = "st,stm32-fmc";
492 clocks = <&rcc STM32_CLOCK(AHB4, 16U)>;
498 compatible = "st,stm32-smbus";
499 #address-cells = <1>;
500 #size-cells = <0>;
506 compatible = "st,stm32-smbus";
507 #address-cells = <1>;
508 #size-cells = <0>;