Lines Matching +full:stm32 +full:- +full:rcc
5 * SPDX-License-Identifier: Apache-2.0
16 compatible = "st,stm32f405", "st,stm32f4", "simple-bus";
18 pinctrl: pin-controller@40020000 {
22 compatible = "st,stm32-gpio";
23 gpio-controller;
24 #gpio-cells = <2>;
26 clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
30 compatible = "st,stm32-gpio";
31 gpio-controller;
32 #gpio-cells = <2>;
34 clocks = <&rcc STM32_CLOCK(AHB1, 6U)>;
38 compatible = "st,stm32-gpio";
39 gpio-controller;
40 #gpio-cells = <2>;
42 clocks = <&rcc STM32_CLOCK(AHB1, 8U)>;
47 compatible = "st,stm32-usart", "st,stm32-uart";
49 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
56 compatible ="st,stm32-uart";
58 clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
65 compatible = "st,stm32-uart";
67 clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
74 compatible = "st,stm32-timers";
76 clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
79 interrupt-names = "global";
84 compatible = "st,stm32-counter";
90 compatible = "st,stm32-timers";
92 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
95 interrupt-names = "global";
100 compatible = "st,stm32-counter";
106 compatible = "st,stm32-timers";
108 clocks = <&rcc STM32_CLOCK(APB2, 1U)>;
111 interrupt-names = "brk", "up", "trgcom", "cc";
116 compatible = "st,stm32-pwm";
118 #pwm-cells = <3>;
122 compatible = "st,stm32-qdec";
124 st,input-filter-level = <NO_FILTER>;
129 compatible = "st,stm32-timers";
131 clocks = <&rcc STM32_CLOCK(APB1, 6U)>;
134 interrupt-names = "global";
139 compatible = "st,stm32-pwm";
141 #pwm-cells = <3>;
145 compatible = "st,stm32-counter";
151 compatible = "st,stm32-timers";
153 clocks = <&rcc STM32_CLOCK(APB1, 7U)>;
156 interrupt-names = "global";
161 compatible = "st,stm32-pwm";
163 #pwm-cells = <3>;
167 compatible = "st,stm32-counter";
173 compatible = "st,stm32-timers";
175 clocks = <&rcc STM32_CLOCK(APB1, 8U)>;
178 interrupt-names = "global";
183 compatible = "st,stm32-pwm";
185 #pwm-cells = <3>;
189 compatible = "st,stm32-counter";
195 compatible = "st,stm32-otghs";
198 interrupt-names = "otghs", "ep1_out", "ep1_in";
199 num-bidir-endpoints = <6>;
200 ram-size = <4096>;
201 maximum-speed = "full-speed";
203 clocks = <&rcc STM32_CLOCK(AHB1, 29U)>,
204 <&rcc STM32_SRC_PLL_Q NO_SEL>;
209 compatible = "st,stm32-bxcan";
212 interrupt-names = "TX", "RX0", "RX1", "SCE";
213 clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
218 compatible = "st,stm32-bxcan";
221 interrupt-names = "TX", "RX0", "RX1", "SCE";
223 clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
224 master-can-reg = <0x40006400>;
229 compatible = "st,stm32-rng";
232 clocks = <&rcc STM32_CLOCK(AHB2, 6U)>;
237 compatible = "zephyr,memory-region", "st,stm32-backup-sram";
239 clocks = <&rcc STM32_CLOCK(AHB1, 18U)>;
240 zephyr,memory-region = "BACKUP_SRAM";
245 compatible = "st,stm32-adc";
247 clocks = <&rcc STM32_CLOCK(APB2, 9U)>;
250 #io-channel-cells = <1>;
255 sampling-times = <3 15 28 56 84 112 144 480>;
256 st,adc-clock-source = "SYNC";
257 st,adc-sequencer = "FULLY_CONFIGURABLE";
258 st,adc-oversampler = "OVERSAMPLER_NONE";
262 compatible = "st,stm32-adc";
264 clocks = <&rcc STM32_CLOCK(APB2, 10U)>;
267 #io-channel-cells = <1>;
272 sampling-times = <3 15 28 56 84 112 144 480>;
273 st,adc-clock-source = "SYNC";
274 st,adc-sequencer = "FULLY_CONFIGURABLE";
275 st,adc-oversampler = "OVERSAMPLER_NONE";
279 compatible = "st,stm32-dac";
281 clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
283 #io-channel-cells = <1>;
288 compatible = "usb-nop-xceiv";
289 #phy-cells = <0>;