Lines Matching +full:dmamux +full:- +full:reg +full:- +full:offset
2 * Copyright 2023-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/clock/nxp_s32k344_clock.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-m7";
20 reg = <0>;
25 compatible = "arm,cortex-m7";
26 reg = <1>;
30 compatible = "arm,armv7m-mpu";
31 reg = <0xe000ed90 0x40>;
37 compatible = "nxp,s32k3-pinctrl";
42 interrupt-parent = <&nvic>;
45 compatible = "zephyr,memory-region", "arm,itcm";
46 reg = <0x00000000 DT_SIZE_K(64)>;
47 zephyr,memory-region = "ITCM";
51 compatible = "zephyr,memory-region", "arm,dtcm";
52 reg = <0x20000000 DT_SIZE_K(128)>;
53 zephyr,memory-region = "DTCM";
57 compatible = "mmio-sram";
58 reg = <0x20400000 DT_SIZE_K(320)>;
65 * need to check if "soc-nv-flash" can be used or a new binding need to be
69 reg = <0x00400000 DT_SIZE_K(4048)>;
73 clock: clock-controller@402c8000 {
74 compatible = "nxp,s32-clock";
75 reg = <0x402c8000 0x4000>,
81 #clock-cells = <1>;
86 reg = <0x40290000 0x10000>;
87 #address-cells = <1>;
88 #size-cells = <1>;
91 compatible = "nxp,s32-siul2-eirq";
92 reg = <0x40290010 0xb4>;
94 interrupt-controller;
95 #interrupt-cells = <2>;
100 compatible = "nxp,s32-gpio";
101 reg = <0x40291702 0x02>, <0x40290240 0x40>;
102 reg-names = "pgpdo", "mscr";
103 interrupt-parent = <&eirq0>;
109 nxp,wkpu-interrupts = <1 9>, <2 4>, <6 19>,
111 gpio-controller;
112 #gpio-cells = <2>;
118 compatible = "nxp,s32-gpio";
119 reg = <0x40291700 0x02>, <0x40290280 0x40>;
120 reg-names = "pgpdo", "mscr";
121 interrupt-parent = <&eirq0>;
125 nxp,wkpu-interrupts = <0 35>, <4 63>, <9 38>,
127 gpio-controller;
128 #gpio-cells = <2>;
134 compatible = "nxp,s32-gpio";
135 reg = <0x40291706 0x02>, <0x402902c0 0x40>;
136 reg-names = "pgpdo", "mscr";
137 interrupt-parent = <&eirq0>;
142 nxp,wkpu-interrupts = <0 11>, <2 12>, <8 29>,
144 gpio-controller;
145 #gpio-cells = <2>;
147 gpio-reserved-ranges = <6 2>;
152 compatible = "nxp,s32-gpio";
153 reg = <0x40291704 0x02>, <0x40290300 0x40>;
154 reg-names = "pgpdo", "mscr";
155 interrupt-parent = <&eirq0>;
159 nxp,wkpu-interrupts = <0 17>, <1 18>, <3 42>,
161 gpio-controller;
162 #gpio-cells = <2>;
168 compatible = "nxp,s32-gpio";
169 reg = <0x4029170a 0x02>, <0x40290340 0x40>;
170 reg-names = "pgpdo", "mscr";
171 interrupt-parent = <&eirq0>;
177 nxp,wkpu-interrupts = <6 7>, <7 6>, <9 14>, <11 22>;
178 gpio-controller;
179 #gpio-cells = <2>;
185 compatible = "nxp,s32-gpio";
186 reg = <0x40291708 0x02>, <0x40290380 0x40>;
187 reg-names = "pgpdo", "mscr";
188 interrupt-parent = <&eirq0>;
192 nxp,wkpu-interrupts = <2 40>, <4 47>, <7 48>,
194 gpio-controller;
195 #gpio-cells = <2>;
201 compatible = "nxp,s32-gpio";
202 reg = <0x4029170e 0x02>, <0x402903c0 0x40>;
203 reg-names = "pgpdo", "mscr";
204 interrupt-parent = <&eirq0>;
210 nxp,wkpu-interrupts = <0 10>, <2 13>, <3 5>,
212 gpio-controller;
213 #gpio-cells = <2>;
219 compatible = "nxp,s32-gpio";
220 reg = <0x4029170c 0x02>, <0x40290400 0x40>;
221 reg-names = "pgpdo", "mscr";
222 interrupt-parent = <&eirq0>;
226 nxp,wkpu-interrupts = <4 58>, <7 54>, <11 55>,
228 gpio-controller;
229 #gpio-cells = <2>;
235 compatible = "nxp,s32-gpio";
236 reg = <0x40291712 0x02>, <0x40290440 0x40>;
237 reg-names = "pgpdo", "mscr";
238 interrupt-parent = <&eirq0>;
244 nxp,wkpu-interrupts = <0 30>, <2 31>, <5 36>,
246 gpio-controller;
247 #gpio-cells = <2>;
253 compatible = "nxp,s32-gpio";
254 reg = <0x40291710 0x02>, <0x40290480 0x40>;
255 reg-names = "pgpdo", "mscr";
256 interrupt-parent = <&eirq0>;
259 nxp,wkpu-interrupts = <0 23>, <2 59>, <5 60>,
261 gpio-controller;
262 #gpio-cells = <2>;
268 compatible = "nxp,s32-gpio";
269 reg = <0x40291716 0x02>, <0x402904c0 0x40>;
270 reg-names = "pgpdo", "mscr";
271 interrupt-parent = <&eirq0>;
276 gpio-controller;
277 #gpio-cells = <2>;
283 compatible = "nxp,s32-gpio";
284 reg = <0x40291714 0x02>, <0x40290500 0x40>;
285 reg-names = "pgpdo", "mscr";
286 gpio-controller;
287 #gpio-cells = <2>;
293 compatible = "nxp,s32-gpio";
294 reg = <0x4029171a 0x02>, <0x40290540 0x40>;
295 reg-names = "pgpdo", "mscr";
296 interrupt-parent = <&eirq0>;
301 gpio-controller;
302 #gpio-cells = <2>;
308 compatible = "nxp,s32-gpio";
309 reg = <0x40291718 0x02>, <0x40290580 0x40>;
310 reg-names = "pgpdo", "mscr";
311 gpio-controller;
312 #gpio-cells = <2>;
319 compatible = "nxp,s32-wkpu";
320 reg = <0x402b4000 0x4000>;
327 reg = <0x40328000 0x4000>;
335 reg = <0x4032c000 0x4000>;
343 reg = <0x40330000 0x4000>;
351 reg = <0x40334000 0x4000>;
359 reg = <0x40338000 0x4000>;
367 reg = <0x4033c000 0x4000>;
375 reg = <0x40340000 0x4000>;
383 reg = <0x40344000 0x4000>;
391 reg = <0x4048c000 0x4000>;
399 reg = <0x40490000 0x4000>;
407 reg = <0x40494000 0x4000>;
415 reg = <0x40498000 0x4000>;
423 reg = <0x4049c000 0x4000>;
431 reg = <0x404a0000 0x4000>;
439 reg = <0x404a4000 0x4000>;
447 reg = <0x404a8000 0x4000>;
454 compatible = "nxp,s32-qspi";
455 reg = <0x404cc000 0x4000>;
456 #address-cells = <1>;
457 #size-cells = <0>;
462 compatible = "nxp,flexcan-fd", "nxp,flexcan";
463 reg = <0x40304000 0x4000>;
465 clk-source = <0>;
467 interrupt-names = "ored", "ored_0_31_mb",
473 compatible = "nxp,flexcan-fd", "nxp,flexcan";
474 reg = <0x40308000 0x4000>;
476 clk-source = <0>;
478 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb";
483 compatible = "nxp,flexcan-fd", "nxp,flexcan";
484 reg = <0x4030c000 0x4000>;
486 clk-source = <0>;
488 interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb";
493 compatible = "nxp,flexcan-fd", "nxp,flexcan";
494 reg = <0x40310000 0x4000>;
496 clk-source = <0>;
498 interrupt-names = "ored", "ored_0_31_mb";
503 compatible = "nxp,flexcan-fd", "nxp,flexcan";
504 reg = <0x40314000 0x4000>;
506 clk-source = <0>;
508 interrupt-names = "ored", "ored_0_31_mb";
513 compatible = "nxp,flexcan-fd", "nxp,flexcan";
514 reg = <0x40318000 0x4000>;
516 clk-source = <0>;
518 interrupt-names = "ored", "ored_0_31_mb";
524 reg = <0x40350000 0x10000>;
526 #address-cells = <1>;
527 #size-cells = <0>;
534 reg = <0x40354000 0x10000>;
536 #address-cells = <1>;
537 #size-cells = <0>;
543 compatible = "nxp,s32-adc-sar";
544 reg = <0x400a0000 0x1000>;
546 #io-channel-cells = <1>;
551 compatible = "nxp,s32-adc-sar";
552 reg = <0x400a4000 0x1000>;
554 #io-channel-cells = <1>;
559 compatible = "nxp,s32-adc-sar";
560 reg = <0x400a8000 0x1000>;
562 #io-channel-cells = <1>;
568 reg = <0x40358000 0x4000>;
571 #address-cells = <1>;
572 #size-cells = <0>;
578 reg = <0x4035c000 0x4000>;
581 #address-cells = <1>;
582 #size-cells = <0>;
588 reg = <0x40360000 0x4000>;
591 #address-cells = <1>;
592 #size-cells = <0>;
598 reg = <0x40364000 0x4000>;
601 #address-cells = <1>;
602 #size-cells = <0>;
608 reg = <0x404bc000 0x4000>;
611 #address-cells = <1>;
612 #size-cells = <0>;
618 reg = <0x404c0000 0x4000>;
621 #address-cells = <1>;
622 #size-cells = <0>;
627 reg = <0x40480000 0x4000>;
628 compatible = "nxp,s32-gmac";
630 interrupt-names = "common", "tx", "rx", "safety";
635 reg = <0x40480200 0x8>;
636 compatible = "nxp,s32-gmac-mdio";
638 #address-cells = <1>;
639 #size-cells = <0>;
643 edma0: dma-controller@4020c000 {
644 compatible = "nxp,mcux-edma";
646 reg = <0x4020c000 0x3000>, <0x40280000 0x4000>, <0x40284000 0x4000>;
647 dma-channels = <32>;
648 dma-requests = <64>;
649 dmamux-reg-offset = <3>;
650 channel-gap = <12 127>;
651 #dma-cells = <2>;
661 no-error-irq;
666 compatible = "nxp,s32-emios";
667 reg = <0x40088000 0x4000>;
671 interrupt-names = "0_0", "0_1", "0_2",
673 internal-cnt = <0xC101FF>;
679 bus-type = "BUS_A";
680 channel-mask = <0x07FFFFF>;
686 bus-type = "BUS_B";
687 channel-mask = <0x00000FE>;
693 bus-type = "BUS_C";
694 channel-mask = <0x0000FE00>;
700 bus-type = "BUS_D";
701 channel-mask = <0x00FE0000>;
707 bus-type = "BUS_F";
708 channel-mask = <0x0BFFFFF>;
714 compatible = "nxp,s32-emios-pwm";
715 #pwm-cells = <3>;
721 compatible = "nxp,s32-emios";
722 reg = <0x4008c000 0x4000>;
726 interrupt-names = "1_0", "1_1", "1_2",
728 internal-cnt = <0xC10101>;
734 bus-type = "BUS_A";
735 channel-mask = <0x07FFFFF>;
741 bus-type = "BUS_B";
742 channel-mask = <0x00000FE>;
748 bus-type = "BUS_C";
749 channel-mask = <0x0000FE00>;
755 bus-type = "BUS_D";
756 channel-mask = <0x00FE0000>;
762 channel-mask = <0x0BFFFFF>;
763 bus-type = "BUS_F";
769 compatible = "nxp,s32-emios-pwm";
770 #pwm-cells = <3>;
776 compatible = "nxp,s32-emios";
777 reg = <0x40090000 0x4000>;
781 interrupt-names = "2_0", "2_1", "2_2",
783 internal-cnt = <0xC10101>;
789 bus-type = "BUS_A";
790 channel-mask = <0x07FFFFF>;
796 bus-type = "BUS_B";
797 channel-mask = <0x00000FE>;
803 bus-type = "BUS_C";
804 channel-mask = <0x0000FE00>;
810 bus-type = "BUS_D";
811 channel-mask = <0x00FE0000>;
817 bus-type = "BUS_F";
818 channel-mask = <0x0BFFFFF>;
824 compatible = "nxp,s32-emios-pwm";
825 #pwm-cells = <3>;
832 reg = <0x40324000 0x4000>;
838 compatible = "nxp,flexio-pwm";
839 #pwm-cells = <3>;
845 compatible = "nxp,s32-lcu";
846 reg = <0x40098000 0x4000>;
851 compatible = "nxp,s32-lcu";
852 reg = <0x4009c000 0x4000>;
857 compatible = "nxp,s32-trgmux";
858 reg = <0x40080000 0x4000>;
863 compatible = "nxp,s32k3-pmc";
864 reg = <0x402e8000 0x4000>;
868 compatible = "nxp,s32-mc-me";
869 reg = <0x402dc000 0x4000>;
873 compatible = "nxp,s32-mc-rgm";
874 reg = <0x4028c000 0x4000>;
875 func-reset-threshold = <0>;
876 dest-reset-threshold = <0>;
880 compatible = "nxp,s32-swt";
881 reg = <0x40270000 0x4000>;
884 service-mode = "fixed";
889 compatible = "nxp,s32-sys-timer";
890 reg = <0x40274000 0x10000>;
897 compatible = "nxp,s32-sys-timer";
898 reg = <0x40474000 0x10000>;
907 arm,num-irq-priority-bits = <4>;