Lines Matching +full:num +full:- +full:inputs
2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
14 #include <zephyr/dt-bindings/inputmux/inputmux_trigger_ports.h>
15 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
16 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
24 #address-cells = <1>;
25 #size-cells = <0>;
28 compatible = "arm,cortex-m33f";
30 #address-cells = <1>;
31 #size-cells = <1>;
32 cpu-power-states = <&idle &suspend>;
35 compatible = "arm,armv8m-mpu";
40 power-states {
43 compatible = "zephyr,power-state";
44 power-state-name = "runtime-idle";
45 min-residency-us = <0>;
46 exit-latency-us = <0>;
48 /* This is the setting for Deep-sleep Mode */
50 compatible = "nxp,pdcfg-power", "zephyr,power-state";
51 power-state-name = "suspend-to-idle";
52 min-residency-us = <500>;
53 exit-latency-us = <120>;
60 deep-sleep-config = <0xC800>,
70 #address-cells = <1>;
71 #size-cells = <1>;
83 compatible = "mmio-sram";
88 compatible = "mmio-sram";
93 compatible = "zephyr,memory-region", "mmio-sram";
95 zephyr,memory-region = "SRAM1";
96 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
109 #address-cells = <1>;
110 #size-cells = <1>;
114 * addresses differ between non-secure (0x40000000) and secure
128 compatible = "nxp,lpc-syscon";
130 #clock-cells = <1>;
134 compatible = "nxp,lpc-iocon";
137 compatible = "nxp,rt-iocon-pinctrl";
143 compatible = "nxp,lpc-syscon";
145 #clock-cells = <1>;
151 #reset-cells = <1>;
157 #reset-cells = <1>;
161 compatible = "nxp,lpc-uid";
166 compatible = "nxp,lpc-gpio";
168 #address-cells = <1>;
169 #size-cells = <0>;
172 compatible = "nxp,lpc-gpio-port";
173 int-source = "pint";
174 gpio-controller;
175 #gpio-cells = <2>;
180 compatible = "nxp,lpc-gpio-port";
181 int-source = "pint";
182 gpio-controller;
183 #gpio-cells = <2>;
188 compatible = "nxp,lpc-gpio-port";
189 gpio-controller;
190 #gpio-cells = <2>;
195 compatible = "nxp,lpc-gpio-port";
196 gpio-controller;
197 #gpio-cells = <2>;
202 compatible = "nxp,lpc-gpio-port";
203 gpio-controller;
204 #gpio-cells = <2>;
209 compatible = "nxp,lpc-gpio-port";
210 gpio-controller;
211 #gpio-cells = <2>;
216 compatible = "nxp,lpc-gpio-port";
217 gpio-controller;
218 #gpio-cells = <2>;
226 interrupt-controller;
227 #interrupt-cells = <1>;
228 #address-cells = <0>;
231 num-lines = <8>;
232 num-inputs = <64>;
236 compatible = "nxp,lpc-flexcomm";
245 compatible = "nxp,lpc-flexcomm";
254 compatible = "nxp,lpc-flexcomm";
263 compatible = "nxp,lpc-flexcomm";
272 compatible = "nxp,lpc-flexcomm";
281 compatible = "nxp,lpc-flexcomm";
290 compatible = "nxp,lpc-flexcomm";
299 compatible = "nxp,lpc-flexcomm";
308 compatible = "nxp,lpc-i2c";
317 compatible = "nxp,lpc-flexcomm";
326 compatible = "nxp,lpc-flexcomm";
335 compatible = "nxp,lpc-flexcomm";
344 compatible = "nxp,lpc-flexcomm";
353 compatible = "nxp,lpc-flexcomm";
362 compatible = "nxp,lpc-flexcomm";
371 compatible = "nxp,dcnano-lcdif";
381 num-bidir-endpoints = <6>;
386 compatible = "nxp,lpc-spi";
392 #address-cells = <1>;
393 #size-cells = <0>;
397 compatible = "nxp,lpc-spi";
403 #address-cells = <1>;
404 #size-cells = <0>;
407 dma0: dma-controller@104000 {
408 compatible = "nxp,lpc-dma";
411 dma-channels = <37>;
412 nxp,dma-num-of-otrigs = <4>;
413 nxp,dma-otrig-base-address = <RT595_DMA0_OTRIG_BASE>;
414 nxp,dma-itrig-base-address = <RT595_DMA0_ITRIG_BASE>;
416 #dma-cells = <1>;
419 dma1: dma-controller@105000 {
420 compatible = "nxp,lpc-dma";
423 dma-channels = <37>;
424 nxp,dma-num-of-otrigs = <4>;
425 nxp,dma-otrig-base-address = <RT595_DMA1_OTRIG_BASE>;
426 nxp,dma-itrig-base-address = <RT595_DMA1_ITRIG_BASE>;
428 #dma-cells = <1>;
432 #address-cells=<1>;
433 #size-cells=<0>;
440 pdmc0: dmic-channel@0 {
441 compatible = "nxp,dmic-channel";
447 pdmc1: dmic-channel@1 {
448 compatible = "nxp,dmic-channel";
454 pdmc2: dmic-channel@2 {
455 compatible = "nxp,dmic-channel";
461 pdmc3: dmic-channel@3 {
462 compatible = "nxp,dmic-channel";
468 pdmc4: dmic-channel@4 {
469 compatible = "nxp,dmic-channel";
475 pdmc5: dmic-channel@5 {
476 compatible = "nxp,dmic-channel";
482 pdmc6: dmic-channel@6 {
483 compatible = "nxp,dmic-channel";
489 pdmc7: dmic-channel@7 {
490 compatible = "nxp,dmic-channel";
498 compatible = "nxp,os-timer";
505 compatible = "nxp,lpc-rtc";
510 compatible = "nxp,lpc-rtc-highres";
516 compatible = "nxp,kinetis-trng";
523 compatible = "nxp,sctimer-pwm";
528 #pwm-cells = <3>;
533 compatible = "nxp,lpc-wwdt";
537 clk-divider = <1>;
541 compatible = "nxp,lpc-wwdt";
545 clk-divider = <1>;
549 compatible = "nxp,imx-usdhc";
554 max-current-330 = <1020>;
555 max-current-180 = <1020>;
556 max-bus-freq = <208000000>;
557 min-bus-freq = <400000>;
561 compatible = "nxp,imx-usdhc";
566 max-current-330 = <1020>;
567 max-current-180 = <1020>;
568 max-bus-freq = <208000000>;
569 min-bus-freq = <400000>;
573 compatible = "nxp,lpc-lpadc";
577 voltage-ref= <1>;
578 calibration-average = <128>;
579 power-level = <0>;
580 offset-value-a = <10>;
581 offset-value-b = <10>;
582 #io-channel-cells = <1>;
589 program-mem = <0x24100000>;
592 #dma-cells = <0>;
596 compatible = "nxp,lpc-ctimer";
600 clk-source = <1>;
608 compatible = "nxp,lpc-ctimer";
612 clk-source = <1>;
620 compatible = "nxp,lpc-ctimer";
624 clk-source = <1>;
632 compatible = "nxp,lpc-ctimer";
636 clk-source = <1>;
644 compatible = "nxp,lpc-ctimer";
648 clk-source = <1>;
656 compatible = "nxp,mipi-dsi-2l";
657 #address-cells = <1>;
658 #size-cells = <0>;
664 clock-names = "dphy", "esc", "pixel";
669 compatible = "nxp,mcux-i3c";
673 clk-divider = <2>;
674 clk-divider-slow = <1>;
675 clk-divider-tc = <1>;
677 #address-cells = <3>;
678 #size-cells = <0>;
682 compatible = "nxp,mbox-imx-mu";
685 rx-channels = <4>;
686 #mbox-cells = <1>;
694 num-channels = <4>;
695 num-bits = <24>;
698 #address-cells = <1>;
699 #size-cells = <0>;
702 compatible = "nxp,mrt-channel";
707 compatible = "nxp,mrt-channel";
712 compatible = "nxp,mrt-channel";
717 compatible = "nxp,mrt-channel";
725 compatible = "nxp,imx-flexspi";
728 #address-cells = <1>;
729 #size-cells = <0>;
734 compatible = "nxp,imx-flexspi";
737 #address-cells = <1>;
738 #size-cells = <0>;
743 arm,num-irq-priority-bits = <3>;