Lines Matching +full:startup +full:- +full:delay +full:- +full:us
2 * Copyright 2023-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/clock/scg_k4.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/pwm/pwm.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
21 zephyr,bt-hci = &hci;
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-m33f";
32 #address-cells = <1>;
33 #size-cells = <1>;
36 compatible = "arm,armv8m-mpu";
43 fmu: memory-controller@50020000 {
45 #address-cells = <1>;
46 #size-cells = <1>;
54 compatible = "soc-nv-flash";
55 write-block-size = <16>;
56 erase-block-size = <8192>;
62 #address-cells = <1>;
63 #size-cells = <1>;
66 compatible = "mmio-sram";
73 #address-cells = <1>;
74 #size-cells = <1>;
77 compatible = "mmio-sram";
83 compatible = "zephyr,memory-region","mmio-sram";
85 zephyr,memory-region = "RetainedMem";
95 #address-cells = <1>;
96 #size-cells = <1>;
101 #address-cells = <1>;
102 #size-cells = <1>;
106 #address-cells = <1>;
107 #size-cells = <1>;
112 #address-cells = <1>;
113 #size-cells = <1>;
120 compatible = "nxp,port-pinctrl";
125 arm,num-irq-priority-bits = <3>;
129 #address-cells = <1>;
130 #size-cells = <1>;
133 compatible = "zephyr,memory-region","mmio-sram";
135 zephyr,memory-region = "rpmsg_sh_mem";
136 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
141 #address-cells = <1>;
142 #size-cells = <1>;
144 scg: clock-controller@1e000 {
145 compatible = "nxp,scg-k4";
147 #clock-cells = <2>;
151 compatible = "nxp,port-pinmux";
157 compatible = "nxp,port-pinmux";
163 compatible = "nxp,port-pinmux";
169 compatible = "nxp,port-pinmux";
192 clock-frequency = <I2C_BITRATE_STANDARD>;
193 #address-cells = <1>;
194 #size-cells = <0>;
203 clock-frequency = <I2C_BITRATE_STANDARD>;
204 #address-cells = <1>;
205 #size-cells = <0>;
217 #address-cells = <1>;
218 #size-cells = <0>;
227 #address-cells = <1>;
228 #size-cells = <0>;
233 compatible = "nxp,kinetis-gpio";
235 gpio-controller;
236 #gpio-cells = <2>;
237 nxp,kinetis-port = <&portd>;
248 compatible = "nxp,kinetis-tpm";
254 #pwm-cells = <3>;
258 compatible = "nxp,kinetis-tpm";
264 #pwm-cells = <3>;
272 clk-source = <1>;
273 clk-divider = <256>;
282 clk-source = <1>;
283 clk-divider = <256>;
291 clock-frequency = <32000>;
292 clk-source = <2>;
302 clock-frequency = <32000>;
303 clk-source = <2>;
312 interrupt-names = "nbu_rx_int";
316 compatible = "nxp,hci-ble";
323 interrupt-names = "common";
325 clk-source = <2>;
330 compatible = "nxp,lpc-lpadc";
334 voltage-ref= <1>;
335 calibration-average = <128>;
337 power-level = <0>;
338 offset-value-a = <0>;
339 offset-value-b = <0>;
340 #io-channel-cells = <1>;
347 regulator-name = "mcxw71-vref";
349 #nxp,reference-cells = <1>;
350 nxp,buffer-startup-delay-us = <400>;
351 nxp,bandgap-startup-time-us = <20>;
352 regulator-min-microvolt = <1000000>;
353 regulator-max-microvolt = <2100000>;
354 nxp,current-compensation-en;
361 compatible = "nxp,kinetis-gpio";
363 gpio-controller;
364 #gpio-cells = <2>;
365 nxp,kinetis-port = <&porta>;
371 compatible = "nxp,kinetis-gpio";
373 gpio-controller;
374 #gpio-cells = <2>;
375 nxp,kinetis-port = <&portb>;
381 compatible = "nxp,kinetis-gpio";
383 gpio-controller;
384 #gpio-cells = <2>;
385 nxp,kinetis-port = <&portc>;