Lines Matching +full:num +full:- +full:inputs

5  * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
15 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
23 		zephyr,flash-controller = &iap;
27 		#address-cells = <1>;
28 		#size-cells = <0>;
31 			compatible = "arm,cortex-m33f";
33 			#address-cells = <1>;
34 			#size-cells = <1>;
37 				compatible = "arm,armv8m-mpu";
45 	#address-cells = <1>;
46 	#size-cells = <1>;
49 		compatible = "mmio-sram";
54 		compatible = "mmio-sram";
59 		compatible = "zephyr,memory-region", "mmio-sram";
61 		zephyr,memory-region = "SRAM1";
65 		compatible = "zephyr,memory-region", "mmio-sram";
67 		zephyr,memory-region = "SRAM2";
71 		compatible = "zephyr,memory-region", "mmio-sram";
73 		zephyr,memory-region = "SRAM4";
77 		compatible = "zephyr,memory-region", "mmio-sram";
79 		zephyr,memory-region = "USB_SRAM";
80 		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
85 	#address-cells = <1>;
86 	#size-cells = <1>;
89 		compatible = "nxp,lpc-syscon";
91 		#clock-cells = <1>;
93 			compatible = "nxp,lpc-syscon-reset";
94 			#reset-cells = <1>;
98 	iap: flash-controller@34000 {
99 		compatible = "nxp,iap-fmc55";
101 		#address-cells = <1>;
102 		#size-cells = <1>;
106 			compatible = "soc-nv-flash";
108 			erase-block-size = <512>;
109 			write-block-size = <512>;
113 			compatible = "nxp,lpc-uid";
118 			compatible = "soc-nv-flash";
124 		compatible = "nxp,lpc-iocon";
126 		#address-cells = <1>;
127 		#size-cells = <1>;
130 			compatible = "nxp,lpc-iocon-pinctrl";
135 		compatible = "nxp,lpc-gpio";
137 		#address-cells = <1>;
138 		#size-cells = <0>;
141 			compatible = "nxp,lpc-gpio-port";
142 			int-source = "pint";
143 			gpio-controller;
144 			#gpio-cells = <2>;
149 			compatible = "nxp,lpc-gpio-port";
150 			int-source = "pint";
151 			gpio-controller;
152 			#gpio-cells = <2>;
160 		interrupt-controller;
161 		#interrupt-cells = <1>;
162 		#address-cells = <0>;
165 		num-lines = <8>;
166 		num-inputs = <64>;
169 	dma0: dma-controller@82000 {
170 		compatible = "nxp,lpc-dma";
173 		dma-channels = <23>;
175 		#dma-cells = <1>;
178 	dma1: dma-controller@a7000 {
179 		compatible = "nxp,lpc-dma";
182 		dma-channels = <10>;
184 		#dma-cells = <1>;
188 		compatible = "nxp,lpc-flexcomm";
197 		compatible = "nxp,lpc-flexcomm";
206 		compatible = "nxp,lpc-flexcomm";
215 		compatible = "nxp,lpc-flexcomm";
224 		compatible = "nxp,lpc-flexcomm";
233 		compatible = "nxp,lpc-flexcomm";
242 		compatible = "nxp,lpc-flexcomm";
251 		compatible = "nxp,lpc-flexcomm";
260 		compatible = "nxp,sctimer-pwm";
266 		#pwm-cells = <3>;
270 		compatible = "nxp,lpc-spi";
271 		/* Enabling cs-gpios below will allow using GPIO CS,
273 		/* cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>,
282 		#address-cells = <1>;
283 		#size-cells = <0>;
287 		compatible = "nxp,lpc-rng";
293 		compatible = "nxp,lpc-wwdt";
297 		clk-divider = <1>;
301 		compatible = "nxp,lpc-lpadc";
305 		clk-divider = <8>;
306 		clk-source = <0>;
307 		voltage-ref= <1>;
308 		calibration-average = <128>;
309 		power-level = <0>;
310 		offset-value-a = <10>;
311 		offset-value-b = <10>;
312 		#io-channel-cells = <1>;
320 		num-bidir-endpoints = <6>;
326 	arm,num-irq-priority-bits = <3>;