Lines Matching +full:0 +full:x80
16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
32 reg = <0x40250000 0x10000>;
40 reg = <0x10000000 DT_SIZE_K(384)>;
46 reg = <0x10060000 DT_SIZE_K(640)>;
53 reg = <0x08000000 DT_SIZE_K(140)>;
58 reg = <0x08023000 DT_SIZE_K(4)>;
64 reg = <0x08024000 DT_SIZE_K(112)>;
73 ranges = <0x40310000 0x40310000 0x2024>;
78 reg = <0x40310000 0x2024>;
85 reg = <0x40320000 0x80>;
86 interrupts = <0 1>;
95 reg = <0x40320080 0x80>;
105 reg = <0x40320100 0x80>;
115 reg = <0x40320180 0x80>;
125 reg = <0x40320200 0x80>;
135 reg = <0x40320280 0x80>;
145 reg = <0x40320300 0x80>;
155 reg = <0x40320380 0x80>;
165 reg = <0x40320400 0x80>;
175 reg = <0x40320480 0x80>;
185 reg = <0x40320500 0x80>;
195 reg = <0x40320580 0x80>;
205 reg = <0x40320600 0x80>;
215 reg = <0x40320680 0x80>;
225 reg = <0x40320700 0x80>;
236 reg = <0x40610000 0x10000>;
238 peripheral-id = <0>;
241 #size-cells = <0>;
245 reg = <0x40620000 0x10000>;
250 #size-cells = <0>;
254 reg = <0x40630000 0x10000>;
259 #size-cells = <0>;
263 reg = <0x40640000 0x10000>;
268 #size-cells = <0>;
272 reg = <0x40650000 0x10000>;
277 #size-cells = <0>;
281 reg = <0x40660000 0x10000>;
286 #size-cells = <0>;
290 reg = <0x40670000 0x10000>;
295 #size-cells = <0>;
299 reg = <0x40680000 0x10000>;
304 #size-cells = <0>;
308 reg = <0x40690000 0x10000>;
313 #size-cells = <0>;
318 reg = <0x40610000 0x10000>;
320 peripheral-id = <0>;
325 reg = <0x40620000 0x10000>;
332 reg = <0x40630000 0x10000>;
339 reg = <0x40640000 0x10000>;
346 reg = <0x40650000 0x10000>;
353 reg = <0x40660000 0x10000>;
360 reg = <0x40670000 0x10000>;
367 reg = <0x40680000 0x10000>;
374 reg = <0x40690000 0x10000>;
382 reg = <0x16000600 0xb>;