Lines Matching full:define
7 #define VALKYRIE_IRQ_H
9 #define SPI_RESERVED7_7 239
10 #define SPI_RESERVED7_6 238
11 #define SPI_RESERVED7_5 237
12 #define SPI_RESERVED7_4 236
13 #define SPI_RESERVED7_3 235
14 #define SPI_RESERVED7_2 234
15 #define SPI_RESERVED7_1 233
16 #define SPI_RESERVED7_0 232
17 #define SPI_RESERVED6_13 231
18 #define SPI_RESERVED6_12 230
19 #define SPI_RESERVED6_11 229
20 #define SPI_RESERVED6_10 228
21 #define SPI_RESERVED6_9 227
22 #define SPI_RESERVED6_8 226
23 #define SPI_RESERVED6_7 225
24 #define SPI_RESERVED6_6 224
25 #define SPI_RESERVED6_5 223
26 #define SPI_RESERVED6_4 222
27 #define SPI_RESERVED6_3 221
28 #define SPI_RESERVED6_2 220
29 #define SPI_RESERVED6_1 219
30 #define SPI_RESERVED6_0 218
31 #define SMU_DMU_AUTH_ERR 217
32 #define SMU_DMU_PAR_ERR 216
33 #define SMU_INTR 215
34 #define IRQ_SMAU_S0_PINS_BUS 214
35 #define IRQ_ROM_S0_PINS_BUS 213
36 #define IRQ_QSPI_S0_PINS_BUS 212
37 #define IRQ_NAND_S0_PINS_BUS 211
38 #define DMA_ARB_ERR_INTR 210
39 #define IRQ_CORESIGHT_M0_PINS_BUS 209
40 #define IRQ_APB_LS3_PINS_BUS 208
41 #define IRQ_APB_LS2_PINS_BUS 207
42 #define IRQ_APB_LS1_PINS_BUS 206
43 #define QSPI_INTERRUPT_O 205
44 #define NAND_INTERRUPT_O 204
45 #define LS_GPIO_INTR 203
46 #define RNG_INTR 202
47 #define WDOG_INTR 201
48 #define UART3_INTR 200
49 #define UART2_INTR 199
50 #define UART1_INTR 198
51 #define UART0_INTR 197
52 #define TIM3_INTR 196
53 #define TIM2_INTR 195
54 #define TIM1_INTR 194
55 #define TIM0_INTR 193
56 #define SPI2_INTR 192
57 #define SPI1_INTR 191
58 #define SPI0_INTR 190
59 #define SMBUS1_INTR 189
60 #define SMBUS0_INTR 188
61 #define MIIM_PAUSE_SCAN_STATUS_CHANGE 187
62 #define MIIM_OP_DONE 186
63 #define MIIM_LINK_SCAN_STATUS_CHANGE 185
64 #define ETIMER_1_TM_INTR3 184
65 #define ETIMER_1_TM_INTR2 183
66 #define ETIMER_1_TM_INTR1 182
67 #define ETIMER_1_TM_INTR0 181
68 #define ETIMER_0_TM_INTR3 180
69 #define ETIMER_0_TM_INTR2 179
70 #define ETIMER_0_TM_INTR1 178
71 #define ETIMER_0_TM_INTR0 177
72 #define DMAC_IRQ_ABORT 176
73 #define DMAC_IRQ7 175
74 #define DMAC_IRQ6 174
75 #define DMAC_IRQ5 173
76 #define DMAC_IRQ4 172
77 #define DMAC_IRQ3 171
78 #define DMAC_IRQ2 170
79 #define DMAC_IRQ1 169
80 #define DMAC_IRQ0 168
81 #define SPI_RESERVED5_7 167
82 #define SPI_RESERVED5_6 166
83 #define SPI_RESERVED5_5 165
84 #define SPI_RESERVED5_4 164
85 #define SPI_RESERVED5_3 163
86 #define SPI_RESERVED5_2 162
87 #define SPI_RESERVED5_1 161
88 #define SPI_RESERVED5_0 160
89 #define DDR1_INTERRUPT3 159
90 #define DDR1_INTERRUPT2 158
91 #define DDR1_INTERRUPT1 157
92 #define DDR1_INTERRUPT0 156
93 #define DDR0_INTERRUPT3 155
94 #define DDR0_INTERRUPT2 154
95 #define DDR0_INTERRUPT1 153
96 #define DDR0_INTERRUPT0 152
97 #define DDR1_TZC_INTERRUPT 151
98 #define DDR0_TZC_INTERRUPT 150
99 #define SPI_RESERVED4_0 149
100 #define PMON_INTERRUPT 148
101 #define SRAM_TZC_INTERRUPT 147
102 #define SCR_SRAM_INTERRUPT 146
103 #define IRQ_GIC_S0_PINS_BUS 145
104 #define IRQ_CRMU_S0_PINS_BUS 144
105 #define IRQ_CRMU_M0_PINS_BUS 143
106 #define IRQ_APB_SCR2_PINS_BUS 142
107 #define IRQ_APB_SCR1_PINS_BUS 141
108 #define SPI_RESERVED3_3 140
109 #define SPI_RESERVED3_2 139
110 #define SPI_RESERVED3_1 138
111 #define SPI_RESERVED3_0 137
112 #define VID_MSTR_RESP_ERR_INTR 136
113 #define PCIE_RM_ERR_INTR 135
114 #define PCIE_ARB_ERR_INTR 134
115 #define PCIE_GLOBAL_ERR_INTR 133
116 #define IRQ_PCIE_NIC_S_PINS_BUS 132
117 #define IRQ_PCIE_S1_PINS_BUS 131
118 #define IRQ_PCIE_S0_PINS_BUS 130
119 #define PAXB1_MSIX_INTR15 129
120 #define PAXB1_MSIX_INTR14 128
121 #define PAXB1_MSIX_INTR13 127
122 #define PAXB1_MSIX_INTR12 126
123 #define PAXB1_MSIX_INTR11 125
124 #define PAXB1_MSIX_INTR10 124
125 #define PAXB1_MSIX_INTR9 123
126 #define PAXB1_MSIX_INTR8 122
127 #define PAXB1_MSIX_INTR7 121
128 #define PAXB1_MSIX_INTR6 120
129 #define PAXB1_MSIX_INTR5 119
130 #define PAXB1_MSIX_INTR4 118
131 #define PAXB1_MSIX_INTR3 117
132 #define PAXB1_MSIX_INTR2 116
133 #define PAXB1_MSIX_INTR1 115
134 #define PAXB1_MSIX_INTR0 114
135 #define PAXB1_GIC_MEM_ERR_INTR 113
136 #define PAXB1_GIC_INTR5 112
137 #define PAXB1_GIC_INTR4 111
138 #define PAXB1_GIC_INTR3 110
139 #define PAXB1_GIC_INTR2 109
140 #define PAXB1_GIC_INTR1 108
141 #define PAXB1_GIC_INTR0 107
142 #define PAXB1_AXI_IBUF_INTR 106
143 #define PAXB0_MSIX_INTR15 105
144 #define PAXB0_MSIX_INTR14 104
145 #define PAXB0_MSIX_INTR13 103
146 #define PAXB0_MSIX_INTR12 102
147 #define PAXB0_MSIX_INTR11 101
148 #define PAXB0_MSIX_INTR10 100
149 #define PAXB0_MSIX_INTR9 99
150 #define PAXB0_MSIX_INTR8 98
151 #define PAXB0_MSIX_INTR7 97
152 #define PAXB0_MSIX_INTR6 96
153 #define PAXB0_MSIX_INTR5 95
154 #define PAXB0_MSIX_INTR4 94
155 #define PAXB0_MSIX_INTR3 93
156 #define PAXB0_MSIX_INTR2 92
157 #define PAXB0_MSIX_INTR1 91
158 #define PAXB0_MSIX_INTR0 90
159 #define PAXB0_GIC_MEM_ERR_INTR 89
160 #define PAXB0_GIC_INTR5 88
161 #define PAXB0_GIC_INTR4 87
162 #define PAXB0_GIC_INTR3 86
163 #define PAXB0_GIC_INTR2 85
164 #define PAXB0_GIC_INTR1 84
165 #define PAXB0_GIC_INTR0 83
166 #define PAXB0_AXI_IBUF_INTR 82
167 #define IHOST_NINTERRIRQ 81
168 #define IHOST_NEXTERRIRQ 80
169 #define IHOST_CRM_INTERRUPT 79
170 #define DEC0_IRQ 78
171 #define DEC1_IRQ 77
172 #define ENC0_IRQ 76
173 #define ENC1_IRQ 75
174 #define ENC2_IRQ 74
175 #define SCL0_IRQ 73
176 #define SCL1_IRQ 72
177 #define SSIM0_AFBC_IRQ_SURFACES_DONE 71
178 #define SSIM0_AFBC_IRQ_SECURE_ID_ERR 70
179 #define SSIM0_AFBC_IRQ_DETLING_ERR 69
180 #define SSIM0_AFBC_IRQ_DECODE_ERR 68
181 #define SSIM0_AFBC_IRQ_CONFIG_SWAP 67
182 #define SSIM0_AFBC_IRQ_AXI_ERR 66
183 #define SSIM0_AFBC_IRQ 65
184 #define SSIM0_IRQ 64
185 #define SSIM1_AFBC_IRQ_SURFACES_DONE 63
186 #define SSIM1_AFBC_IRQ_SECURE_ID_ERR 62
187 #define SSIM1_AFBC_IRQ_DETLING_ERR 61
188 #define SSIM1_AFBC_IRQ_DECODE_ERR 60
189 #define SSIM1_AFBC_IRQ_CONFIG_SWAP 59
190 #define SSIM1_AFBC_IRQ_AXI_ERR 58
191 #define SSIM1_AFBC_IRQ 57
192 #define SSIM1_IRQ 56
193 #define SSIM2_AFBC_IRQ_SURFACES_DONE 55
194 #define SSIM2_AFBC_IRQ_SECURE_ID_ERR 54
195 #define SSIM2_AFBC_IRQ_DETLING_ERR 53
196 #define SSIM2_AFBC_IRQ_DECODE_ERR 52
197 #define SSIM2_AFBC_IRQ_CONFIG_SWAP 51
198 #define SSIM2_AFBC_IRQ_AXI_ERR 50
199 #define SSIM2_AFBC_IRQ 49
200 #define SSIM2_IRQ 48
201 #define PCIE1_INB_PERSTB_EVENT 47
202 #define PCIE0_INB_PERSTB_EVENT 46
203 #define PCIE1_PERSTB_EVENT 45
204 #define PCIE0_PERSTB_EVENT 44
205 #define MCU_NS_MAILBOX3_EVENT 43
206 #define MCU_NS_MAILBOX2_EVENT 42
207 #define MCU_NS_MAILBOX1_EVENT 41
208 #define MCU_NS_MAILBOX0_EVENT 40
209 #define RESERVED_39 39
210 #define RESERVED_38 38
211 #define RESERVED_37 37
212 #define RESERVED_36 36
213 #define RESERVED_35 35
214 #define MCU_COMB_IDM_INTR 34
215 #define MCU_TIMER2_INTR 33
216 #define MCU_TIMER1_INTR 32
217 #define MCU_MAILBOX_EVENT 31
218 #define MCU_IPROC_STANDBYWFI_EVENT 30
219 #define MCU_IPROC_STANDBYWFE_EVENT 29
220 #define RESERVED_28 28
221 #define RESERVED_27 27
222 #define RESERVED_26 26
223 #define MCU_MAILBOX1_EVENT 25
224 #define RESERVED_24 24
225 #define RESERVED_23 23
226 #define RESERVED_22 22
227 #define RESERVED_21 21
228 #define RESERVED_20 20
229 #define RESERVED_19 19
230 #define GIC_ECC_ERR_INITR 18
231 #define GIC_AXI_ERR_INITR 17
232 #define AVS_TEMP_RESET_INTR 16
233 #define AVS_MONITOR_INTR 15
234 #define MCU_SECURITY_INTR 14
235 #define RESERVED_13 13
236 #define RESERVED_12 12
237 #define MCU_RESET_LOG_INTR 11
238 #define MCU_POWER_LOG_INTR 10
239 #define MCU_ERROR_LOG_INTR 9
240 #define MCU_WDOG_INTR 8
241 #define MCU_TIMER_INTR 7
242 #define MCU_SMBUS_INTR 6
243 #define RESERVED_5 5
244 #define RESERVED_4 4
245 #define CHIPCOMMONG_WDOG_RESET 3
246 #define MCU_AON_GPIO_INTR 2
247 #define MCU_AON_UART_INTR 1
248 #define RESERVED_0 0