Lines Matching +full:reg +full:- +full:names
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv6-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
16 adc-0 = &adc0;
18 port-a = &porta;
19 port-b = &portb;
20 port-c = &portc;
22 sercom-0 = &sercom0;
23 sercom-1 = &sercom1;
24 sercom-2 = &sercom2;
25 sercom-3 = &sercom3;
27 tcc-0 = &tcc0;
28 tcc-1 = &tcc1;
29 tcc-2 = &tcc2;
35 zephyr,flash-controller = &nvmctrl;
39 #address-cells = <1>;
40 #size-cells = <0>;
43 compatible = "arm,cortex-m0+";
44 reg = <0>;
51 compatible = "mmio-sram";
55 compatible = "atmel,sam0-id";
56 reg = <0x0080A00C 0x4>,
64 compatible = "atmel,sam0-nvmctrl";
65 reg = <0x41004000 0x22>;
68 #address-cells = <1>;
69 #size-cells = <1>;
71 lock-regions = <16>;
74 compatible = "soc-nv-flash";
76 write-block-size = <4>;
81 compatible = "atmel,samc2x-mclk";
82 reg = <0x40000800 0x400>;
84 #clock-cells = <2>;
88 compatible = "atmel,samc2x-gclk";
89 reg = <0x40001c00 0x400>;
91 #clock-cells = <1>;
95 compatible = "atmel,sam0-eic";
96 reg = <0x40002800 0x1C>;
101 compatible = "atmel,sam0-pinmux";
102 reg = <0x41000000 0x80>;
106 compatible = "atmel,sam0-watchdog";
107 reg = <0x40002000 9>;
112 compatible = "atmel,sam0-dmac";
113 reg = <0x41006000 0x50>;
117 #dma-cells = <2>;
121 compatible = "atmel,sam0-adc";
122 reg = <0x42004400 0x30>;
124 interrupt-names = "resrdy";
126 clock-names = "GCLK", "MCLK";
129 #io-channel-cells = <1>;
136 compatible = "atmel,sam0-sercom";
137 reg = <0x42000400 0x40>;
140 clock-names = "GCLK", "MCLK";
145 compatible = "atmel,sam0-sercom";
146 reg = <0x42000800 0x40>;
149 clock-names = "GCLK", "MCLK";
154 compatible = "atmel,sam0-sercom";
155 reg = <0x42000c00 0x40>;
158 clock-names = "GCLK", "MCLK";
163 compatible = "atmel,sam0-sercom";
164 reg = <0x42001000 0x40>;
167 clock-names = "GCLK", "MCLK";
172 compatible = "atmel,sam0-tcc";
173 reg = <0x42002400 0x80>;
176 clock-names = "GCLK", "MCLK";
180 counter-size = <24>;
184 compatible = "atmel,sam0-tcc";
185 reg = <0x42002800 0x80>;
188 clock-names = "GCLK", "MCLK";
192 counter-size = <24>;
196 compatible = "atmel,sam0-tcc";
197 reg = <0x42002c00 0x80>;
200 clock-names = "GCLK", "MCLK";
204 counter-size = <16>;
208 compatible = "atmel,sam0-pinctrl";
211 #address-cells = <1>;
212 #size-cells = <1>;
215 compatible = "atmel,sam0-gpio";
216 reg = <0x41000000 0x80>;
218 #atmel,pin-cells = <2>;
219 #gpio-cells = <2>;
221 gpio-controller;
225 compatible = "atmel,sam0-gpio";
226 reg = <0x41000080 0x80>;
228 #atmel,pin-cells = <2>;
229 #gpio-cells = <2>;
231 gpio-controller;
235 compatible = "atmel,sam0-gpio";
236 reg = <0x41000100 0x80>;
238 #atmel,pin-cells = <2>;
239 #gpio-cells = <2>;
241 gpio-controller;
246 compatible = "atmel,sam0-rtc";
247 reg = <0x40002400 0x1C>;
251 clock-generator = <0>;
257 arm,num-irq-priority-bits = <2>;