Lines Matching +full:0 +full:x80
16 adc-0 = &adc0;
22 sercom-0 = &sercom0;
27 tcc-0 = &tcc0;
40 #size-cells = <0>;
42 cpu0: cpu@0 {
44 reg = <0>;
56 reg = <0x0080A00C 0x4>,
57 <0x0080A040 0x4>,
58 <0x0080A044 0x4>,
59 <0x0080A048 0x4>;
65 reg = <0x41004000 0x22>;
66 interrupts = <6 0>;
73 flash0: flash@0 {
82 reg = <0x40000800 0x400>;
89 reg = <0x40001c00 0x400>;
96 reg = <0x40002800 0x1C>;
97 interrupts = <3 0>;
102 reg = <0x41000000 0x80>;
107 reg = <0x40002000 9>;
108 interrupts = <1 0>;
113 reg = <0x41006000 0x50>;
114 interrupts = <7 0>;
122 reg = <0x42004400 0x30>;
123 interrupts = <25 0>;
125 clocks = <&gclk 33>, <&mclk 0x1c 17>;
131 gclk = <0>;
137 reg = <0x42000400 0x40>;
138 interrupts = <9 0>;
139 clocks = <&gclk 19>, <&mclk 0x1c 1>;
146 reg = <0x42000800 0x40>;
147 interrupts = <10 0>;
148 clocks = <&gclk 20>, <&mclk 0x1c 2>;
155 reg = <0x42000c00 0x40>;
156 interrupts = <11 0>;
157 clocks = <&gclk 21>, <&mclk 0x1c 3>;
164 reg = <0x42001000 0x40>;
165 interrupts = <12 0>;
166 clocks = <&gclk 22>, <&mclk 0x1c 4>;
173 reg = <0x42002400 0x80>;
174 interrupts = <17 0>;
175 clocks = <&gclk 28>, <&mclk 0x1c 9>;
185 reg = <0x42002800 0x80>;
186 interrupts = <18 0>;
187 clocks = <&gclk 28>, <&mclk 0x1c 10>;
197 reg = <0x42002c00 0x80>;
198 interrupts = <19 0>;
199 clocks = <&gclk 29>, <&mclk 0x1c 11>;
209 ranges = <0x41000000 0x41000000 0x180>;
216 reg = <0x41000000 0x80>;
226 reg = <0x41000080 0x80>;
236 reg = <0x41000100 0x80>;
247 reg = <0x40002400 0x1C>;
248 interrupts = <3 0>;
251 clock-generator = <0>;