Lines Matching +full:max32 +full:- +full:pinctrl
2 * Copyright (c) 2023-2024 Analog Devices, Inc.
4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/clock/adi_max32_clock.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/adc/adc.h>
18 zephyr,flash-controller = &flc0;
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-m4f";
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <DT_FREQ_M(100)>;
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <DT_FREQ_M(60)>;
48 compatible = "fixed-clock";
49 #clock-cells = <0>;
50 clock-frequency = <DT_FREQ_K(8)>;
55 compatible = "fixed-clock";
56 #clock-cells = <0>;
57 clock-frequency = <7372800>;
62 compatible = "fixed-clock";
63 #clock-cells = <0>;
64 clock-frequency = <32768>;
69 compatible = "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <DT_FREQ_M(32)>;
78 compatible = "mmio-sram";
83 compatible = "adi,max32-flash-controller";
86 #address-cells = <1>;
87 #size-cells = <1>;
91 compatible = "soc-nv-flash";
93 write-block-size = <16>;
94 erase-block-size = <8192>;
98 gcr: clock-controller@40000000 {
100 compatible = "adi,max32-gcr";
101 #clock-cells = <2>;
103 sysclk-prescaler = <1>;
108 compatible = "adi,max32-i2c";
110 #address-cells = <1>;
111 #size-cells = <0>;
112 clock-frequency = <I2C_BITRATE_STANDARD>;
119 compatible = "adi,max32-i2c";
121 #address-cells = <1>;
122 #size-cells = <0>;
123 clock-frequency = <I2C_BITRATE_STANDARD>;
130 compatible = "adi,max32-i2c";
132 #address-cells = <1>;
133 #size-cells = <0>;
134 clock-frequency = <I2C_BITRATE_STANDARD>;
140 pinctrl: pin-controller@40008000 { label
141 compatible = "adi,max32-pinctrl";
142 #address-cells = <1>;
143 #size-cells = <1>;
148 compatible = "adi,max32-gpio";
149 gpio-controller;
150 #gpio-cells = <2>;
158 compatible = "adi,max32-gpio";
159 gpio-controller;
160 #gpio-cells = <2>;
168 compatible = "adi,max32-uart";
171 clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
177 compatible = "adi,max32-uart";
180 clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
186 compatible = "adi,max32-uart";
189 clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
195 compatible = "adi,max32-trng";
202 compatible = "adi,max32-watchdog";
206 clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
211 compatible = "adi,max32-adc-10b", "adi,max32-adc";
214 channel-count = <17>;
215 #io-channel-cells = <1>;
218 vref-mv = <1220>;
223 compatible = "adi,max32-timer";
228 clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
231 compatible = "adi,max32-counter";
235 compatible = "adi,max32-pwm";
237 #pwm-cells = <3>;
242 compatible = "adi,max32-timer";
247 clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
250 compatible = "adi,max32-counter";
254 compatible = "adi,max32-pwm";
256 #pwm-cells = <3>;
261 compatible = "adi,max32-timer";
266 clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
269 compatible = "adi,max32-counter";
273 compatible = "adi,max32-pwm";
275 #pwm-cells = <3>;
280 compatible = "adi,max32-timer";
285 clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
288 compatible = "adi,max32-counter";
292 compatible = "adi,max32-pwm";
294 #pwm-cells = <3>;
299 compatible = "adi,max32-rtc-counter";
308 arm,num-irq-priority-bits = <3>;