Lines Matching refs:SWT_CR
20 #define SWT_CR 0x0 macro
122 REG_WRITE(SWT_CR, REG_READ(SWT_CR) | SWT_CR_HLK(1U)); in swt_lock()
125 REG_WRITE(SWT_CR, REG_READ(SWT_CR) | SWT_CR_SLK(1U)); in swt_lock()
138 if (FIELD_GET(SWT_CR_HLK_MASK, REG_READ(SWT_CR)) != 0U) { in swt_unlock()
142 } else if (FIELD_GET(SWT_CR_SLK_MASK, REG_READ(SWT_CR)) != 0U) { in swt_unlock()
146 if (!WAIT_FOR(FIELD_GET(SWT_CR_SLK_MASK, REG_READ(SWT_CR) != 0), in swt_unlock()
152 REG_WRITE(SWT_CR, REG_READ(SWT_CR) | SWT_CR_SLK(1U)); in swt_unlock()
182 reg_val = REG_READ(SWT_CR); in swt_nxp_s32_setup()
184 REG_WRITE(SWT_CR, reg_val | in swt_nxp_s32_setup()
198 REG_WRITE(SWT_CR, REG_READ(SWT_CR) | SWT_CR_WEN(1U)); in swt_nxp_s32_setup()
210 if (!FIELD_GET(SWT_CR_WEN_MASK, REG_READ(SWT_CR))) { in swt_nxp_s32_disable()
221 REG_WRITE(SWT_CR, REG_READ(SWT_CR) & ~SWT_CR_WEN_MASK); in swt_nxp_s32_disable()
331 FIELD_GET(SWT_CR_ITR_MASK, REG_READ(SWT_CR))) { in swt_nxp_s32_isr()
358 REG_WRITE(SWT_CR, in swt_nxp_s32_init()