Lines Matching +full:reset +full:- +full:pulse +full:- +full:length

1 /* SPDX-License-Identifier: Apache-2.0 */
19  * and programmed based on user-defined options.
21  * The generated interrupt is passed to an interrupt controller. The generated reset is passed to a
22  * reset controller, which in turn generates a reset for the components in the system. The WDT may
23  * be reset independently to the other components.
52 /* Generate a system reset
57  * by the time a second timeout occurs then generate a system reset
62  * Reset pulse length
116  * bits WDT_CNT_WIDTH - 1 to 0
195  * Describes the initial timeout period that is available directly after reset. It controls the
196  * reset value of the register. If WDT_HC_TOP is 1, then the default initial time period is the
202  * Selects the timeout period that is available directly after reset. It controls the reset value
209  * The reset pulse length that is available directly after reset.
241  * of 2 from 2^16 to 2^(WDT_CNT_WIDTH-1). When this parameter is set to 0, the user must define the
242  * timeout period range (2^8 to 2^(WDT_CNT_WIDTH)-1) using the WDT_USER_TOP_(i) parameter.
252  * Configures the reset pulse length to be hard coded.
268  * Describes the output response mode that is available directly after reset. Indicates the output
269  * response the WDT gives if a zero count is reached; that is, a system reset if equals 0 and
270  * an interrupt followed by a system reset, if equals 1. If WDT_HC_RMOD is 1, then default response
276  * Configures the WDT to be enabled from reset. If this setting is 1, the WDT is always enabled and
295  * followed by a 16-bit unsigned number.
316  * Selects whether watchdog should generate interrupt on the first timeout (true) or reset system
321  *		false = Generate a system reset,
323  *		       timeout occurs then generate a system reset
339  * @brief Set reset pulse length.
342  * @param pclk_cycles Reset pulse length selector (2 to 256 pclk cycles)
408 	current_counter_value &= (1 << (wdt_counter_width - 1));  in dw_wdt_current_counter_value_register_get()
471  * @brief Get the default value of the timeout range that is selected after reset.
474  * @return Default timeout range after reset
482  * @brief Get the default value of the timeout counter that is set after reset.
504  * @brief Describes the initial timeout period that is available directly after reset.
506  * It controls the reset value of the register. If WDT_HC_TOP is 1, then the default initial time
520  * Selects the timeout period that is available directly after reset. It controls the reset value
533  * @brief The reset pulse length that is available directly after reset.
536  * @return Reset pulse length
576  * of 2 from 2^16 to 2^(WDT_CNT_WIDTH-1). When this parameter is set to 0, the user must define the
577  * timeout period range (2^8 to 2^(WDT_CNT_WIDTH)-1) using the WDT_USER_TOP_(i) parameter.
603  * @brief Checks if reset pulse length is hardcoded.
606  * @return 0x0 (PROGRAMMABLE): Reset pulse length is programmable
607  *	   0x1 (HARDCODED): Reset pulse length is hardcoded
644  * Describes the output response mode that is available directly after reset. Indicates the output
645  * response the WDT gives if a zero count is reached; that is, a system reset if equals 0 and an
646  * interrupt followed by a system reset, if equals 1. If WDT_HC_RMOD is 1, then default response
650  * @return 0x0 (DISABLED): System reset only
651  *	   0x1 (ENABLED): Interrupt and system reset
659  * @brief Checks if watchdog is enabled from reset
665  * @return 0x0 (DISABLED): Watchdog timer disabled on reset
666  *	   0x1 (ENABLED): Watchdog timer enabled on reset