Lines Matching +full:connected +full:- +full:ground
4 * SPDX-License-Identifier: Apache-2.0
63 const struct max3421e_config *config = dev->config; in max3421e_read_hirq()
92 ret = spi_transceive_dt(&config->dt_spi, &tx, &rx); in max3421e_read_hirq()
94 priv->hirq = hirq; in max3421e_read_hirq()
113 const struct max3421e_config *config = dev->config; in max3421e_write_byte()
125 return spi_write_dt(&config->dt_spi, &tx); in max3421e_write_byte()
133 const struct max3421e_config *config = dev->config; in max3421e_write()
151 return spi_write_dt(&config->dt_spi, &tx); in max3421e_write()
156 struct uhc_data *data = dev->data; in max3421e_lock()
158 return k_mutex_lock(&data->mutex, K_FOREVER); in max3421e_lock()
163 struct uhc_data *data = dev->data; in max3421e_unlock()
165 return k_mutex_unlock(&data->mutex); in max3421e_unlock()
174 priv->hien &= ~hint; in max3421e_hien_disable()
176 return max3421e_write_byte(dev, MAX3421E_REG_HIEN, priv->hien); in max3421e_hien_disable()
186 if (priv->addr != addr) { in max3421e_peraddr()
194 priv->addr = addr; in max3421e_peraddr()
205 uint8_t ep_idx = MAX3421E_EP(priv->hxfr); in max3421e_tgl_update()
207 if (priv->hxfr & MAX3421E_OUTNIN) { in max3421e_tgl_update()
208 if (priv->hrsl & MAX3421E_SNDTOGRD) { in max3421e_tgl_update()
209 priv->tog_out |= BIT(ep_idx); in max3421e_tgl_update()
211 priv->tog_out &= ~BIT(ep_idx); in max3421e_tgl_update()
214 if (priv->hrsl & MAX3421E_RCVTOGRD) { in max3421e_tgl_update()
215 priv->tog_in |= BIT(ep_idx); in max3421e_tgl_update()
217 priv->tog_in &= ~BIT(ep_idx); in max3421e_tgl_update()
221 LOG_DBG("tog_in 0x%02x tog_out 0x%02x last-hxfr 0x%02x hrsl 0x%02x", in max3421e_tgl_update()
222 priv->tog_in, priv->tog_out, priv->hxfr, priv->hrsl); in max3421e_tgl_update()
235 priv->tog_in |= BIT(0); in max3421e_tgl_next()
236 priv->tog_out |= BIT(0); in max3421e_tgl_next()
240 hctl = (priv->tog_out & BIT(ep_idx)) ? MAX3421E_SNDTOG1 : in max3421e_tgl_next()
243 hctl = (priv->tog_in & BIT(ep_idx)) ? MAX3421E_RCVTOG1 : in max3421e_tgl_next()
255 if (priv->hxfr != hxfr) { in max3421e_hxfr_start()
261 priv->hxfr = hxfr; in max3421e_hxfr_start()
268 return max3421e_write_byte(dev, MAX3421E_REG_HXFR, priv->hxfr); in max3421e_hxfr_start()
284 len = MIN(MAX3421E_MAX_EP_SIZE, buf->len); in max3421e_xfer_data()
287 ret = max3421e_write(dev, MAX3421E_REG_SNDFIFO, buf->data, len); in max3421e_xfer_data()
313 struct net_buf *buf = xfer->buf; in max3421e_xfer_control()
318 return max3421e_hxfr_start(dev, priv->hxfr); in max3421e_xfer_control()
322 if (xfer->stage == UHC_CONTROL_STAGE_SETUP) { in max3421e_xfer_control()
325 xfer->setup_pkt, sizeof(xfer->setup_pkt)); in max3421e_xfer_control()
338 if (buf != NULL && xfer->stage == UHC_CONTROL_STAGE_DATA) { in max3421e_xfer_control()
340 return max3421e_xfer_data(dev, buf, xfer->ep); in max3421e_xfer_control()
343 if (xfer->stage == UHC_CONTROL_STAGE_STATUS) { in max3421e_xfer_control()
345 if (USB_EP_DIR_IS_IN(xfer->ep)) { in max3421e_xfer_control()
354 return -EINVAL; in max3421e_xfer_control()
362 struct net_buf *buf = xfer->buf; in max3421e_xfer_bulk()
366 return max3421e_hxfr_start(dev, priv->hxfr); in max3421e_xfer_bulk()
371 return -ENODATA; in max3421e_xfer_bulk()
374 return max3421e_xfer_data(dev, buf, xfer->ep); in max3421e_xfer_bulk()
380 const uint8_t hirq = priv->hirq; in max3421e_schedule_xfer()
381 const uint8_t hrsl = priv->hrsl; in max3421e_schedule_xfer()
383 if (priv->last_xfer == NULL) { in max3421e_schedule_xfer()
386 priv->last_xfer = uhc_xfer_get_next(dev); in max3421e_schedule_xfer()
387 if (priv->last_xfer == NULL) { in max3421e_schedule_xfer()
392 LOG_DBG("Next transfer %p", priv->last_xfer); in max3421e_schedule_xfer()
393 ret = max3421e_peraddr(dev, priv->last_xfer->addr); in max3421e_schedule_xfer()
400 if (priv->last_xfer->timeout) { in max3421e_schedule_xfer()
401 priv->last_xfer->timeout--; in max3421e_schedule_xfer()
411 if (USB_EP_GET_IDX(priv->last_xfer->ep) == 0) { in max3421e_schedule_xfer()
412 return max3421e_xfer_control(dev, priv->last_xfer, hrsl); in max3421e_schedule_xfer()
415 return max3421e_xfer_bulk(dev, priv->last_xfer, hrsl); in max3421e_schedule_xfer()
422 if (priv->last_xfer) { in max3421e_xfer_drop_active()
423 uhc_xfer_return(dev, priv->last_xfer, err); in max3421e_xfer_drop_active()
424 priv->last_xfer = NULL; in max3421e_xfer_drop_active()
431 struct uhc_transfer *const xfer = priv->last_xfer; in max3421e_hrslt_success()
432 struct net_buf *buf = xfer->buf; in max3421e_hrslt_success()
438 switch (MAX3421E_HXFR_TYPE(priv->hxfr)) { in max3421e_hrslt_success()
440 if (xfer->buf != NULL) { in max3421e_hrslt_success()
441 xfer->stage = UHC_CONTROL_STAGE_DATA; in max3421e_hrslt_success()
443 xfer->stage = UHC_CONTROL_STAGE_STATUS; in max3421e_hrslt_success()
463 if (buf->len == 0) { in max3421e_hrslt_success()
464 LOG_INF("hrslt bulk out %u", buf->len); in max3421e_hrslt_success()
465 if (xfer->ep == USB_CONTROL_EP_OUT) { in max3421e_hrslt_success()
466 xfer->stage = UHC_CONTROL_STAGE_STATUS; in max3421e_hrslt_success()
480 bc - net_buf_tailroom(buf)); in max3421e_hrslt_success()
494 if (xfer->ep == USB_CONTROL_EP_IN) { in max3421e_hrslt_success()
495 xfer->stage = UHC_CONTROL_STAGE_STATUS; in max3421e_hrslt_success()
506 priv->last_xfer = NULL; in max3421e_hrslt_success()
519 struct uhc_transfer *const xfer = priv->last_xfer; in max3421e_handle_hxfrdn()
520 const uint8_t hrsl = priv->hrsl; in max3421e_handle_hxfrdn()
525 return -ENODATA; in max3421e_handle_hxfrdn()
534 * TODO: Transfer cancel request (xfer->cancel) in max3421e_handle_hxfrdn()
537 if (xfer->timeout == 0) { in max3421e_handle_hxfrdn()
538 max3421e_xfer_drop_active(dev, -ETIMEDOUT); in max3421e_handle_hxfrdn()
543 max3421e_xfer_drop_active(dev, -EPIPE); in max3421e_handle_hxfrdn()
553 max3421e_xfer_drop_active(dev, -EINVAL); in max3421e_handle_hxfrdn()
554 ret = -EINVAL; in max3421e_handle_hxfrdn()
564 const uint8_t jk = priv->hrsl & MAX3421E_JKSTATUS_MASK; in max3421e_handle_condet()
568 * JSTATUS:KSTATUS 0:0 - SE0 in max3421e_handle_condet()
569 * JSTATUS:KSTATUS 0:1 - K (Resume) in max3421e_handle_condet()
570 * JSTATUS:KSTATUS 1:0 - J (Idle) in max3421e_handle_condet()
578 /* Device connected */ in max3421e_handle_condet()
583 /* Device connected */ in max3421e_handle_condet()
594 if (atomic_test_and_clear_bit(&priv->state, in max3421e_bus_event()
600 if (atomic_test_and_clear_bit(&priv->state, in max3421e_bus_event()
612 err = max3421e_read_hirq(dev, MAX3421E_REG_HRSL, &priv->hrsl, 1, true); in max3421e_update_hrsl_hirq()
614 priv->hirq &= priv->hien | MAX3421E_RCVDAV; in max3421e_update_hrsl_hirq()
615 LOG_DBG("HIRQ 0x%02x HRSLT %d", priv->hirq, MAX3421E_HRSLT(priv->hrsl)); in max3421e_update_hrsl_hirq()
628 const uint8_t hirq = priv->hirq; in max3421e_handle_bus_irq()
669 k_sem_take(&priv->irq_sem, K_FOREVER); in uhc_max3421e_thread()
683 if (priv->hirq & MAX3421E_HXFRDN) { in uhc_max3421e_thread()
689 if (priv->hirq & MAX3421E_FRAME) { in uhc_max3421e_thread()
690 schedule = HRSLT_IS_BUSY(priv->hrsl) ? false : true; in uhc_max3421e_thread()
694 if (priv->hirq & ~(MAX3421E_FRAME | MAX3421E_HXFRDN)) { in uhc_max3421e_thread()
702 err = max3421e_clear_hirq(dev, priv->hirq); in uhc_max3421e_thread()
725 k_sem_give(&priv->irq_sem); in max3421e_gpio_cb()
733 if (priv->mode & MAX3421E_SOFKAENAB) { in max3421e_sof_enable()
734 return -EALREADY; in max3421e_sof_enable()
737 priv->mode |= MAX3421E_SOFKAENAB; in max3421e_sof_enable()
739 return max3421e_write_byte(dev, MAX3421E_REG_MODE, priv->mode); in max3421e_sof_enable()
747 if (!(priv->mode & MAX3421E_SOFKAENAB)) { in max3421e_bus_suspend()
748 return -EALREADY; in max3421e_bus_suspend()
751 priv->hien |= MAX3421E_SUSDN; in max3421e_bus_suspend()
752 priv->mode &= ~MAX3421E_SOFKAENAB; in max3421e_bus_suspend()
754 uint8_t tmp[3] = {MAX3421E_SUSDN, priv->hien, priv->mode}; in max3421e_bus_suspend()
765 if (atomic_test_bit(&priv->state, MAX3421E_STATE_BUS_RESUME)) { in max3421e_bus_reset()
766 return -EBUSY; in max3421e_bus_reset()
770 atomic_set_bit(&priv->state, MAX3421E_STATE_BUS_RESET); in max3421e_bus_reset()
775 /* Signal bus resume event, 20ms K-state + low-speed EOP */
781 if (atomic_test_bit(&priv->state, MAX3421E_STATE_BUS_RESET)) { in max3421e_bus_resume()
782 return -EBUSY; in max3421e_bus_resume()
786 atomic_set_bit(&priv->state, MAX3421E_STATE_BUS_RESUME); in max3421e_bus_resume()
806 const struct max3421e_config *config = dev->config; in max3421e_reset()
809 if (config->dt_rst.port) { in max3421e_reset()
810 gpio_pin_set_dt(&config->dt_rst, 1); in max3421e_reset()
811 gpio_pin_set_dt(&config->dt_rst, 0); in max3421e_reset()
836 return -EIO; in max3421e_reset()
841 /* Full-Duplex SPI, INT pin edge active, GPX pin signals SOF */ in max3421e_pinctl_setup()
859 return -EIO; in max3421e_pinctl_setup()
873 * host mode, connect internal D+ and D- pulldown resistors to ground in max3421e_mode_setup()
894 return -EIO; in max3421e_mode_setup()
897 priv->mode = mode; in max3421e_mode_setup()
925 return -EIO; in max3421e_hien_setup()
928 priv->hien = hien; in max3421e_hien_setup()
953 return -EIO; in max3421e_enable_int_output()
1002 rev, priv->mode, priv->hien); in uhc_max3421e_init()
1004 priv->addr = 0; in uhc_max3421e_init()
1006 /* Sample bus if device is already connected */ in uhc_max3421e_init()
1030 const struct max3421e_config *config = dev->config; in max3421e_driver_init()
1031 struct uhc_data *data = dev->data; in max3421e_driver_init()
1032 struct max3421e_data *priv = data->priv; in max3421e_driver_init()
1035 if (config->dt_rst.port) { in max3421e_driver_init()
1036 if (!gpio_is_ready_dt(&config->dt_rst)) { in max3421e_driver_init()
1038 config->dt_rst.port->name); in max3421e_driver_init()
1039 return -EIO; in max3421e_driver_init()
1042 ret = gpio_pin_configure_dt(&config->dt_rst, in max3421e_driver_init()
1046 config->dt_rst.pin); in max3421e_driver_init()
1051 if (!spi_is_ready_dt(&config->dt_spi)) { in max3421e_driver_init()
1052 LOG_ERR("SPI device %s not ready", config->dt_spi.bus->name); in max3421e_driver_init()
1053 return -EIO; in max3421e_driver_init()
1056 if (!gpio_is_ready_dt(&config->dt_int)) { in max3421e_driver_init()
1057 LOG_ERR("GPIO device %s not ready", config->dt_int.port->name); in max3421e_driver_init()
1058 return -EIO; in max3421e_driver_init()
1061 ret = gpio_pin_configure_dt(&config->dt_int, GPIO_INPUT); in max3421e_driver_init()
1063 LOG_ERR("Failed to configure GPIO pin %u", config->dt_int.pin); in max3421e_driver_init()
1067 gpio_init_callback(&priv->gpio_cb, max3421e_gpio_cb, in max3421e_driver_init()
1068 BIT(config->dt_int.pin)); in max3421e_driver_init()
1069 ret = gpio_add_callback(config->dt_int.port, &priv->gpio_cb); in max3421e_driver_init()
1074 ret = gpio_pin_interrupt_configure_dt(&config->dt_int, in max3421e_driver_init()
1080 k_mutex_init(&data->mutex); in max3421e_driver_init()