Lines Matching +full:active +full:- +full:range +full:- +full:x +full:- +full:max
4 * SPDX-License-Identifier: Apache-2.0
78 const struct device *dev = priv->dev; in HAL_PCD_ResetCallback()
79 const struct udc_stm32_config *cfg = dev->config; in HAL_PCD_ResetCallback()
82 /* Re-Enable control endpoints */ in HAL_PCD_ResetCallback()
84 if (ep && ep->stat.enabled) { in HAL_PCD_ResetCallback()
85 HAL_PCD_EP_Open(&priv->pcd, USB_CONTROL_EP_OUT, cfg->ep0_mps, in HAL_PCD_ResetCallback()
90 if (ep && ep->stat.enabled) { in HAL_PCD_ResetCallback()
91 HAL_PCD_EP_Open(&priv->pcd, USB_CONTROL_EP_IN, cfg->ep0_mps, in HAL_PCD_ResetCallback()
95 udc_submit_event(priv->dev, UDC_EVT_RESET, 0); in HAL_PCD_ResetCallback()
102 udc_submit_event(priv->dev, UDC_EVT_VBUS_READY, 0); in HAL_PCD_ConnectCallback()
109 udc_submit_event(priv->dev, UDC_EVT_VBUS_REMOVED, 0); in HAL_PCD_DisconnectCallback()
116 udc_set_suspended(priv->dev, true); in HAL_PCD_SuspendCallback()
117 udc_submit_event(priv->dev, UDC_EVT_SUSPEND, 0); in HAL_PCD_SuspendCallback()
124 udc_set_suspended(priv->dev, false); in HAL_PCD_ResumeCallback()
125 udc_submit_event(priv->dev, UDC_EVT_RESUME, 0); in HAL_PCD_ResumeCallback()
136 return -ENOMEM; in usbd_ctrl_feed_dout()
139 k_fifo_put(&cfg->fifo, buf); in usbd_ctrl_feed_dout()
141 HAL_PCD_EP_Receive(&priv->pcd, cfg->addr, buf->data, buf->size); in usbd_ctrl_feed_dout()
149 struct usb_setup_packet *setup = (void *)priv->pcd.Setup; in HAL_PCD_SetupStageCallback()
150 const struct device *dev = priv->dev; in HAL_PCD_SetupStageCallback()
162 memcpy(buf->data, setup, 8); in HAL_PCD_SetupStageCallback()
167 if (!buf->len) { in HAL_PCD_SetupStageCallback()
171 if ((setup->bmRequestType == 0) && in HAL_PCD_SetupStageCallback()
172 (setup->bRequest == USB_SREQ_SET_ADDRESS)) { in HAL_PCD_SetupStageCallback()
174 HAL_PCD_SetAddress(&priv->pcd, setup->wValue); in HAL_PCD_SetupStageCallback()
180 if (err == -ENOMEM) { in HAL_PCD_SetupStageCallback()
194 udc_submit_event(priv->dev, UDC_EVT_SOF, 0); in HAL_PCD_SOFCallback()
201 const struct udc_stm32_config *cfg = dev->config; in udc_stm32_tx()
205 LOG_DBG("TX ep 0x%02x len %u", ep, buf->len); in udc_stm32_tx()
211 data = buf->data; in udc_stm32_tx()
212 len = buf->len; in udc_stm32_tx()
215 len = MIN(cfg->ep0_mps, buf->len); in udc_stm32_tx()
218 buf->data += len; in udc_stm32_tx()
219 buf->len -= len; in udc_stm32_tx()
221 status = HAL_PCD_EP_Transmit(&priv->pcd, ep, data, len); in udc_stm32_tx()
223 LOG_ERR("HAL_PCD_EP_Transmit failed(0x%02x), %d", ep, (int)status); in udc_stm32_tx()
224 return -EIO; in udc_stm32_tx()
245 LOG_DBG("RX ep 0x%02x len %u", ep, buf->size); in udc_stm32_rx()
251 status = HAL_PCD_EP_Receive(&priv->pcd, ep, buf->data, buf->size); in udc_stm32_rx()
253 LOG_ERR("HAL_PCD_EP_Receive failed(0x%02x), %d", ep, (int)status); in udc_stm32_rx()
254 return -EIO; in udc_stm32_rx()
266 const struct device *dev = priv->dev; in HAL_PCD_DataOutStageCallback()
270 LOG_DBG("DataOut ep 0x%02x", ep); in HAL_PCD_DataOutStageCallback()
276 LOG_ERR("ep 0x%02x queue is empty", ep); in HAL_PCD_DataOutStageCallback()
306 const struct device *dev = priv->dev; in HAL_PCD_DataInStageCallback()
310 LOG_DBG("DataIn ep 0x%02x", ep); in HAL_PCD_DataInStageCallback()
319 if (ep == USB_CONTROL_EP_IN && buf->len) { in HAL_PCD_DataInStageCallback()
320 const struct udc_stm32_config *cfg = dev->config; in HAL_PCD_DataInStageCallback()
321 uint32_t len = MIN(cfg->ep0_mps, buf->len); in HAL_PCD_DataInStageCallback()
323 HAL_PCD_EP_Transmit(&priv->pcd, ep, buf->data, len); in HAL_PCD_DataInStageCallback()
325 buf->len -= len; in HAL_PCD_DataInStageCallback()
326 buf->data += len; in HAL_PCD_DataInStageCallback()
333 HAL_PCD_EP_Transmit(&priv->pcd, ep, buf->data, 0); in HAL_PCD_DataInStageCallback()
384 HAL_PCD_IRQHandler((PCD_HandleTypeDef *)&priv->pcd); in udc_stm32_irq()
392 if (priv->clk_enable && priv->clk_enable()) { in udc_stm32_init()
394 return -EIO; in udc_stm32_init()
397 priv->pcd_prepare(dev); in udc_stm32_init()
399 status = HAL_PCD_Init(&priv->pcd); in udc_stm32_init()
402 return -EIO; in udc_stm32_init()
405 HAL_PCD_Stop(&priv->pcd); in udc_stm32_init()
414 const struct udc_stm32_config *cfg = dev->config; in udc_stm32_mem_init()
416 priv->occupied_mem = cfg->pma_offset; in udc_stm32_mem_init()
424 const struct udc_stm32_config *cfg = dev->config; in udc_stm32_ep_mem_config()
427 size = MIN(udc_mps_ep_size(ep), cfg->ep_mps); in udc_stm32_ep_mem_config()
430 priv->occupied_mem -= size; in udc_stm32_ep_mem_config()
434 if (priv->occupied_mem + size >= cfg->dram_size) { in udc_stm32_ep_mem_config()
435 LOG_ERR("Unable to allocate FIFO for 0x%02x", ep->addr); in udc_stm32_ep_mem_config()
436 return -ENOMEM; in udc_stm32_ep_mem_config()
440 HAL_PCDEx_PMAConfig(&priv->pcd, ep->addr, PCD_SNG_BUF, in udc_stm32_ep_mem_config()
441 priv->occupied_mem); in udc_stm32_ep_mem_config()
443 priv->occupied_mem += size; in udc_stm32_ep_mem_config()
451 const struct udc_stm32_config *cfg = dev->config; in udc_stm32_mem_init()
454 LOG_DBG("DRAM size: %ub", cfg->dram_size); in udc_stm32_mem_init()
456 if (cfg->ep_mps % 4 || cfg->ep0_mps % 4) { in udc_stm32_mem_init()
457 LOG_ERR("Not a 32-bit word multiple: ep0(%u)|ep(%u)", in udc_stm32_mem_init()
458 cfg->ep0_mps, cfg->ep_mps); in udc_stm32_mem_init()
465 words = MAX(0x40, cfg->ep_mps / 4); in udc_stm32_mem_init()
466 HAL_PCDEx_SetRxFiFo(&priv->pcd, words); in udc_stm32_mem_init()
467 priv->occupied_mem = words * 4; in udc_stm32_mem_init()
470 HAL_PCDEx_SetTxFiFo(&priv->pcd, 0, cfg->ep0_mps / 4); in udc_stm32_mem_init()
471 priv->occupied_mem += cfg->ep0_mps; in udc_stm32_mem_init()
474 for (unsigned int i = 1U; i < cfg->num_endpoints; i++) { in udc_stm32_mem_init()
475 HAL_PCDEx_SetTxFiFo(&priv->pcd, i, 0); in udc_stm32_mem_init()
484 const struct udc_stm32_config *cfg = dev->config; in udc_stm32_ep_mem_config()
487 if (!(ep->addr & USB_EP_DIR_IN) || !USB_EP_GET_IDX(ep->addr)) { in udc_stm32_ep_mem_config()
491 words = MIN(udc_mps_ep_size(ep), cfg->ep_mps) / 4; in udc_stm32_ep_mem_config()
495 if (priv->occupied_mem >= (words * 4)) { in udc_stm32_ep_mem_config()
496 priv->occupied_mem -= (words * 4); in udc_stm32_ep_mem_config()
498 HAL_PCDEx_SetTxFiFo(&priv->pcd, USB_EP_GET_IDX(ep->addr), 0); in udc_stm32_ep_mem_config()
502 if (cfg->dram_size - priv->occupied_mem < words * 4) { in udc_stm32_ep_mem_config()
503 LOG_ERR("Unable to allocate FIFO for 0x%02x", ep->addr); in udc_stm32_ep_mem_config()
504 return -ENOMEM; in udc_stm32_ep_mem_config()
507 HAL_PCDEx_SetTxFiFo(&priv->pcd, USB_EP_GET_IDX(ep->addr), words); in udc_stm32_ep_mem_config()
509 priv->occupied_mem += words * 4; in udc_stm32_ep_mem_config()
518 const struct udc_stm32_config *cfg = dev->config; in udc_stm32_enable()
526 status = HAL_PCD_Start(&priv->pcd); in udc_stm32_enable()
529 return -EIO; in udc_stm32_enable()
533 USB_EP_TYPE_CONTROL, cfg->ep0_mps, 0); in udc_stm32_enable()
535 LOG_ERR("Failed enabling ep 0x%02x", USB_CONTROL_EP_OUT); in udc_stm32_enable()
540 USB_EP_TYPE_CONTROL, cfg->ep0_mps, 0); in udc_stm32_enable()
542 LOG_ERR("Failed enabling ep 0x%02x", USB_CONTROL_EP_IN); in udc_stm32_enable()
546 irq_enable(priv->irq); in udc_stm32_enable()
560 return -EIO; in udc_stm32_disable()
565 return -EIO; in udc_stm32_disable()
568 status = HAL_PCD_Stop(&priv->pcd); in udc_stm32_disable()
571 return -EIO; in udc_stm32_disable()
582 status = HAL_PCD_DeInit(&priv->pcd); in udc_stm32_shutdown()
588 if (priv->clk_disable && priv->clk_disable()) { in udc_stm32_shutdown()
593 if (irq_is_enabled(priv->irq)) { in udc_stm32_shutdown()
594 irq_disable(priv->irq); in udc_stm32_shutdown()
607 status = HAL_PCD_SetAddress(&priv->pcd, addr); in udc_stm32_set_address()
609 LOG_ERR("HAL_PCD_SetAddress failed(0x%02x), %d", in udc_stm32_set_address()
611 return -EIO; in udc_stm32_set_address()
622 status = HAL_PCD_ActivateRemoteWakeup(&priv->pcd); in udc_stm32_host_wakeup()
625 return -EIO; in udc_stm32_host_wakeup()
628 /* Must be active from 1ms to 15ms as per reference manual. */ in udc_stm32_host_wakeup()
631 status = HAL_PCD_DeActivateRemoteWakeup(&priv->pcd); in udc_stm32_host_wakeup()
633 return -EIO; in udc_stm32_host_wakeup()
647 LOG_DBG("Enable ep 0x%02x", ep_cfg->addr); in udc_stm32_ep_enable()
649 switch (ep_cfg->attributes & USB_EP_TRANSFER_TYPE_MASK) { in udc_stm32_ep_enable()
663 return -EINVAL; in udc_stm32_ep_enable()
671 status = HAL_PCD_EP_Open(&priv->pcd, ep_cfg->addr, in udc_stm32_ep_enable()
674 LOG_ERR("HAL_PCD_EP_Open failed(0x%02x), %d", in udc_stm32_ep_enable()
675 ep_cfg->addr, (int)status); in udc_stm32_ep_enable()
676 return -EIO; in udc_stm32_ep_enable()
688 LOG_DBG("Disable ep 0x%02x", ep->addr); in udc_stm32_ep_disable()
690 status = HAL_PCD_EP_Close(&priv->pcd, ep->addr); in udc_stm32_ep_disable()
692 LOG_ERR("HAL_PCD_EP_Close failed(0x%02x), %d", in udc_stm32_ep_disable()
693 ep->addr, (int)status); in udc_stm32_ep_disable()
694 return -EIO; in udc_stm32_ep_disable()
706 LOG_DBG("Halt ep 0x%02x", cfg->addr); in udc_stm32_ep_set_halt()
708 status = HAL_PCD_EP_SetStall(&priv->pcd, cfg->addr); in udc_stm32_ep_set_halt()
710 LOG_ERR("HAL_PCD_EP_SetStall failed(0x%02x), %d", in udc_stm32_ep_set_halt()
711 cfg->addr, (int)status); in udc_stm32_ep_set_halt()
712 return -EIO; in udc_stm32_ep_set_halt()
724 LOG_DBG("Clear halt for ep 0x%02x", cfg->addr); in udc_stm32_ep_clear_halt()
726 status = HAL_PCD_EP_ClrStall(&priv->pcd, cfg->addr); in udc_stm32_ep_clear_halt()
728 LOG_ERR("HAL_PCD_EP_ClrStall failed(0x%02x), %d", in udc_stm32_ep_clear_halt()
729 cfg->addr, (int)status); in udc_stm32_ep_clear_halt()
730 return -EIO; in udc_stm32_ep_clear_halt()
742 LOG_DBG("Flush ep 0x%02x", cfg->addr); in udc_stm32_ep_flush()
744 status = HAL_PCD_EP_Flush(&priv->pcd, cfg->addr); in udc_stm32_ep_flush()
746 LOG_ERR("HAL_PCD_EP_Flush failed(0x%02x), %d", in udc_stm32_ep_flush()
747 cfg->addr, (int)status); in udc_stm32_ep_flush()
748 return -EIO; in udc_stm32_ep_flush()
765 if (USB_EP_DIR_IS_IN(epcfg->addr)) { in udc_stm32_ep_enqueue()
766 ret = udc_stm32_tx(dev, epcfg->addr, buf); in udc_stm32_ep_enqueue()
768 ret = udc_stm32_rx(dev, epcfg->addr, buf); in udc_stm32_ep_enqueue()
783 buf = udc_buf_get_all(dev, epcfg->addr); in udc_stm32_ep_dequeue()
785 udc_submit_ep_event(dev, buf, -ECONNABORTED); in udc_stm32_ep_dequeue()
788 udc_ep_set_busy(dev, epcfg->addr, false); in udc_stm32_ep_dequeue()
798 if (priv->pcd.Init.speed == USBD_HS_SPEED) { in udc_stm32_device_speed()
803 if (priv->pcd.Init.speed == USBD_FS_SPEED) { in udc_stm32_device_speed()
829 /* ----------------- Instance/Device specific data ----------------- */
892 * If max-speed is not passed via DT, set it to USB controller's in usb_dc_stm32_get_maximum_speed()
903 if (!strncmp(USB_MAXIMUM_SPEED, "high-speed", 10)) { in usb_dc_stm32_get_maximum_speed()
905 } else if (!strncmp(USB_MAXIMUM_SPEED, "full-speed", 10)) { in usb_dc_stm32_get_maximum_speed()
925 const struct udc_stm32_config *cfg = dev->config; in priv_pcd_prepare()
927 memset(&priv->pcd, 0, sizeof(priv->pcd)); in priv_pcd_prepare()
930 priv->pcd.Init.dev_endpoints = cfg->num_endpoints; in priv_pcd_prepare()
931 priv->pcd.Init.ep0_mps = cfg->ep0_mps; in priv_pcd_prepare()
932 priv->pcd.Init.speed = PCD_SPEED_FULL; in priv_pcd_prepare()
936 priv->pcd.Instance = USB; in priv_pcd_prepare()
938 priv->pcd.Instance = USB_DRD_FS; in priv_pcd_prepare()
940 priv->pcd.Init.speed = usb_dc_stm32_get_maximum_speed(); in priv_pcd_prepare()
942 priv->pcd.Instance = USB_OTG_HS; in priv_pcd_prepare()
944 priv->pcd.Instance = USB_OTG_FS; in priv_pcd_prepare()
949 priv->pcd.Init.phy_itface = USB_OTG_HS_EMBEDDED_PHY; in priv_pcd_prepare()
951 priv->pcd.Init.phy_itface = USB_OTG_ULPI_PHY; in priv_pcd_prepare()
953 priv->pcd.Init.phy_itface = PCD_PHY_EMBEDDED; in priv_pcd_prepare()
965 return -ENODEV; in priv_clock_enable()
976 /* Check that power range is 1 or 2 */ in priv_clock_enable()
978 LOG_ERR("Wrong Power range to use USB OTG HS"); in priv_clock_enable()
979 return -EIO; in priv_clock_enable()
1014 LOG_INF("PWR not active yet"); in priv_clock_enable()
1023 return -EIO; in priv_clock_enable()
1029 return -EIO; in priv_clock_enable()
1039 return -EIO; in priv_clock_enable()
1044 return -ENOTSUP; in priv_clock_enable()
1065 /* Disable ULPI interface (for external high-speed PHY) clock in sleep/low-power mode. in priv_clock_enable()
1098 return -EIO; in priv_clock_disable()
1122 const struct udc_stm32_config *cfg = dev->config; in udc_stm32_driver_init0()
1123 struct udc_data *data = dev->data; in udc_stm32_driver_init0()
1130 ep_cfg_out[i].caps.mps = cfg->ep0_mps; in udc_stm32_driver_init0()
1135 ep_cfg_out[i].caps.mps = cfg->ep_mps; in udc_stm32_driver_init0()
1150 ep_cfg_in[i].caps.mps = cfg->ep0_mps; in udc_stm32_driver_init0()
1166 data->caps.rwup = true; in udc_stm32_driver_init0()
1167 data->caps.out_ack = false; in udc_stm32_driver_init0()
1168 data->caps.mps0 = UDC_MPS0_64; in udc_stm32_driver_init0()
1170 priv->dev = dev; in udc_stm32_driver_init0()
1171 priv->irq = UDC_STM32_IRQ; in udc_stm32_driver_init0()
1172 priv->clk_enable = priv_clock_enable; in udc_stm32_driver_init0()
1173 priv->clk_disable = priv_clock_disable; in udc_stm32_driver_init0()
1174 priv->pcd_prepare = priv_pcd_prepare; in udc_stm32_driver_init0()
1203 return -EINVAL; in udc_stm32_driver_init0()
1207 return -EIO; in udc_stm32_driver_init0()