Lines Matching +full:master +full:- +full:access +full:- +full:mask
4 * SPDX-License-Identifier: Apache-2.0
44 /* Minimum RX FIFO size in 32-bit words considering the largest used OUT packet
49 /* Default Rx FIFO size in 32-bit words calculated to support High-Speed with:
57 /* TX FIFO0 depth in 32-bit words (used by control IN endpoint)
63 /* Get Data FIFO access register */
105 /* Transfer triggers (IN on bits 0-15, OUT on bits 16-31) */
107 /* Finished transactions (IN on bits 0-15, OUT on bits 16-31) */
143 const struct udc_dwc2_config *const config = dev->config; in dwc2_init_pinctrl()
144 const struct pinctrl_dev_config *const pcfg = config->pcfg; in dwc2_init_pinctrl()
172 const struct udc_dwc2_config *const config = dev->config; in dwc2_get_base()
174 return config->base; in dwc2_get_base()
211 return (mem_addr_t)&base->out_ep[ep_idx].doepctl; in dwc2_get_dxepctl_reg()
213 return (mem_addr_t)&base->in_ep[ep_idx].diepctl; in dwc2_get_dxepctl_reg()
221 mem_addr_t reg = (mem_addr_t)&base->in_ep[idx].dtxfsts; in dwc2_ftx_avail()
236 return priv->max_pktcnt; in dwc2_get_iept_pktctn()
247 return priv->max_xfersize; in dwc2_get_iept_xfersize()
254 mem_addr_t grstctl_reg = (mem_addr_t)&base->grstctl; in dwc2_flush_rx_fifo()
264 mem_addr_t grstctl_reg = (mem_addr_t)&base->grstctl; in dwc2_flush_tx_fifo()
274 /* Return TX FIFOi depth in 32-bit words (i = f_idx + 1) */
280 dieptxf = sys_read32((mem_addr_t)&base->dieptxf[f_idx]); in dwc2_get_txfdep()
291 dieptxf = sys_read32((mem_addr_t)&base->dieptxf[f_idx]); in dwc2_get_txfaddr()
306 sys_write32(dieptxf, (mem_addr_t)&base->dieptxf[f_idx]); in dwc2_set_txf()
314 mem_addr_t reg = (mem_addr_t)&base->daintmsk; in dwc2_set_epint()
315 uint8_t ep_idx = USB_EP_GET_IDX(cfg->addr); in dwc2_set_epint()
318 if (USB_EP_DIR_IS_IN(cfg->addr)) { in dwc2_set_epint()
333 switch (cfg->attributes & USB_EP_TRANSFER_TYPE_MASK) { in dwc2_ep_is_periodic()
345 return (cfg->attributes & USB_EP_TRANSFER_TYPE_MASK) == USB_EP_TYPE_ISO; in dwc2_ep_is_iso()
373 uint8_t ep_idx = USB_EP_GET_IDX(cfg->addr); in dwc2_tx_fifo_write()
375 mem_addr_t dieptsiz_reg = (mem_addr_t)&base->in_ep[ep_idx].dieptsiz; in dwc2_tx_fifo_write()
377 mem_addr_t diepctl_reg = (mem_addr_t)&base->in_ep[ep_idx].diepctl; in dwc2_tx_fifo_write()
378 mem_addr_t diepint_reg = (mem_addr_t)&base->in_ep[ep_idx].diepint; in dwc2_tx_fifo_write()
382 const uint32_t addnl = USB_MPS_ADDITIONAL_TRANSACTIONS(cfg->mps); in dwc2_tx_fifo_write()
391 * (micro-)frame at a time. in dwc2_tx_fifo_write()
393 len = MIN(buf->len, USB_MPS_TO_TPL(cfg->mps)); in dwc2_tx_fifo_write()
398 len = buf->len; in dwc2_tx_fifo_write()
401 if (!priv->bufferdma) { in dwc2_tx_fifo_write()
421 cfg->addr, spcavail, len); in dwc2_tx_fifo_write()
422 return -EAGAIN; in dwc2_tx_fifo_write()
437 len = ROUND_DOWN(max_xfersize, USB_MPS_TO_TPL(cfg->mps)); in dwc2_tx_fifo_write()
455 cfg->addr, len, pktcnt, addnl); in dwc2_tx_fifo_write()
456 priv->tx_len[ep_idx] = len; in dwc2_tx_fifo_write()
466 if (priv->bufferdma) { in dwc2_tx_fifo_write()
467 if (!dwc2_dma_buffer_ok_to_use(dev, buf->data, len, cfg->mps)) { in dwc2_tx_fifo_write()
472 return -ENOTSUP; in dwc2_tx_fifo_write()
475 sys_write32((uint32_t)buf->data, in dwc2_tx_fifo_write()
476 (mem_addr_t)&base->in_ep[ep_idx].diepdma); in dwc2_tx_fifo_write()
478 sys_cache_data_flush_range(buf->data, len); in dwc2_tx_fifo_write()
488 return -ENOENT; in dwc2_tx_fifo_write()
493 * specify on which (micro-)frame the data should be sent. in dwc2_tx_fifo_write()
495 if (priv->sof_num & 1) { in dwc2_tx_fifo_write()
509 if (!priv->bufferdma) { in dwc2_tx_fifo_write()
510 const uint8_t *src = buf->data; in dwc2_tx_fifo_write()
531 pktcnt--; in dwc2_tx_fifo_write()
533 len -= pktlen; in dwc2_tx_fifo_write()
549 /* FIFO access is always in 32-bit words */ in dwc2_read_fifo()
566 for (uint32_t n = 0; n < DIV_ROUND_UP(size - len, d); n++) { in dwc2_read_fifo()
580 uint8_t ep_idx = USB_EP_GET_IDX(cfg->addr); in dwc2_prep_rx()
581 mem_addr_t doeptsiz_reg = (mem_addr_t)&base->out_ep[ep_idx].doeptsiz; in dwc2_prep_rx()
593 xfersize = USB_MPS_TO_TPL(cfg->mps); in dwc2_prep_rx()
594 pktcnt = 1 + USB_MPS_ADDITIONAL_TRANSACTIONS(cfg->mps); in dwc2_prep_rx()
601 /* Set the Even/Odd (micro-)frame appropriately */ in dwc2_prep_rx()
602 if (priv->sof_num & 1) { in dwc2_prep_rx()
611 if (xfersize > priv->max_xfersize) { in dwc2_prep_rx()
612 xfersize = ROUND_DOWN(priv->max_xfersize, USB_MPS_TO_TPL(cfg->mps)); in dwc2_prep_rx()
615 pktcnt = DIV_ROUND_UP(xfersize, USB_MPS_EP_SIZE(cfg->mps)); in dwc2_prep_rx()
621 if (cfg->addr == USB_CONTROL_EP_OUT) { in dwc2_prep_rx()
626 priv->rx_siz[ep_idx] = doeptsiz; in dwc2_prep_rx()
629 if (priv->bufferdma) { in dwc2_prep_rx()
630 if (!dwc2_dma_buffer_ok_to_use(dev, buf->data, xfersize, cfg->mps)) { in dwc2_prep_rx()
637 sys_write32((uint32_t)buf->data, in dwc2_prep_rx()
638 (mem_addr_t)&base->out_ep[ep_idx].doepdma); in dwc2_prep_rx()
640 sys_cache_data_invd_range(buf->data, xfersize); in dwc2_prep_rx()
645 LOG_INF("Prepare RX 0x%02x doeptsiz 0x%x", cfg->addr, doeptsiz); in dwc2_prep_rx()
653 buf = udc_buf_peek(dev, cfg->addr); in dwc2_handle_xfer_next()
658 if (USB_EP_DIR_IS_OUT(cfg->addr)) { in dwc2_handle_xfer_next()
665 cfg->addr, err); in dwc2_handle_xfer_next()
667 buf = udc_buf_get(dev, cfg->addr); in dwc2_handle_xfer_next()
668 if (udc_submit_ep_event(dev, buf, -ECONNREFUSED)) { in dwc2_handle_xfer_next()
676 udc_ep_set_busy(dev, cfg->addr, true); in dwc2_handle_xfer_next()
686 return -ENOMEM; in dwc2_ctrl_feed_dout()
705 return -ENODATA; in dwc2_handle_evt_setup()
708 net_buf_add_mem(buf, priv->setup, sizeof(priv->setup)); in dwc2_handle_evt_setup()
710 LOG_HEXDUMP_DBG(buf->data, buf->len, "setup"); in dwc2_handle_evt_setup()
719 LOG_DBG("s:%p|feed for -out-", buf); in dwc2_handle_evt_setup()
725 if (err == -ENOMEM) { in dwc2_handle_evt_setup()
729 LOG_DBG("s:%p|feed for -in-status", buf); in dwc2_handle_evt_setup()
732 if (err == -ENOMEM) { in dwc2_handle_evt_setup()
741 if (err == -ENOMEM) { in dwc2_handle_evt_setup()
757 buf = udc_buf_get(dev, cfg->addr); in dwc2_handle_evt_dout()
759 LOG_ERR("No buffer queued for ep 0x%02x", cfg->addr); in dwc2_handle_evt_dout()
760 return -ENODATA; in dwc2_handle_evt_dout()
763 udc_ep_set_busy(dev, cfg->addr, false); in dwc2_handle_evt_dout()
765 if (cfg->addr == USB_CONTROL_EP_OUT) { in dwc2_handle_evt_dout()
767 /* s-in-status finished */ in dwc2_handle_evt_dout()
772 if (err == -ENOMEM) { in dwc2_handle_evt_dout()
786 if (err == -ENOMEM) { in dwc2_handle_evt_dout()
809 buf = udc_buf_peek(dev, cfg->addr); in dwc2_handle_evt_din()
811 LOG_ERR("No buffer for ep 0x%02x", cfg->addr); in dwc2_handle_evt_din()
812 udc_submit_event(dev, UDC_EVT_ERROR, -ENOBUFS); in dwc2_handle_evt_din()
813 return -ENOBUFS; in dwc2_handle_evt_din()
816 if (buf->len) { in dwc2_handle_evt_din()
821 if (cfg->addr == USB_CONTROL_EP_IN && udc_ep_buf_has_zlp(buf)) { in dwc2_handle_evt_din()
826 buf = udc_buf_get(dev, cfg->addr); in dwc2_handle_evt_din()
827 udc_ep_set_busy(dev, cfg->addr, false); in dwc2_handle_evt_din()
829 if (cfg->addr == USB_CONTROL_EP_IN) { in dwc2_handle_evt_din()
855 const struct udc_dwc2_config *const config = dev->config; in dwc2_backup_registers()
856 struct usb_dwc2_reg *const base = config->base; in dwc2_backup_registers()
858 struct dwc2_reg_backup *backup = &priv->backup; in dwc2_backup_registers()
860 backup->gotgctl = sys_read32((mem_addr_t)&base->gotgctl); in dwc2_backup_registers()
861 backup->gahbcfg = sys_read32((mem_addr_t)&base->gahbcfg); in dwc2_backup_registers()
862 backup->gusbcfg = sys_read32((mem_addr_t)&base->gusbcfg); in dwc2_backup_registers()
863 backup->gintmsk = sys_read32((mem_addr_t)&base->gintmsk); in dwc2_backup_registers()
864 backup->grxfsiz = sys_read32((mem_addr_t)&base->grxfsiz); in dwc2_backup_registers()
865 backup->gnptxfsiz = sys_read32((mem_addr_t)&base->gnptxfsiz); in dwc2_backup_registers()
866 backup->gi2cctl = sys_read32((mem_addr_t)&base->gi2cctl); in dwc2_backup_registers()
867 backup->glpmcfg = sys_read32((mem_addr_t)&base->glpmcfg); in dwc2_backup_registers()
868 backup->gdfifocfg = sys_read32((mem_addr_t)&base->gdfifocfg); in dwc2_backup_registers()
870 for (uint8_t i = 1U; i < priv->ineps; i++) { in dwc2_backup_registers()
871 backup->dieptxf[i - 1] = sys_read32((mem_addr_t)&base->dieptxf[i - 1]); in dwc2_backup_registers()
874 backup->dcfg = sys_read32((mem_addr_t)&base->dcfg); in dwc2_backup_registers()
875 backup->dctl = sys_read32((mem_addr_t)&base->dctl); in dwc2_backup_registers()
876 backup->diepmsk = sys_read32((mem_addr_t)&base->diepmsk); in dwc2_backup_registers()
877 backup->doepmsk = sys_read32((mem_addr_t)&base->doepmsk); in dwc2_backup_registers()
878 backup->daintmsk = sys_read32((mem_addr_t)&base->daintmsk); in dwc2_backup_registers()
881 uint32_t epdir = usb_dwc2_get_ghwcfg1_epdir(priv->ghwcfg1, i); in dwc2_backup_registers()
884 backup->diepctl[i] = sys_read32((mem_addr_t)&base->in_ep[i].diepctl); in dwc2_backup_registers()
885 if (backup->diepctl[i] & USB_DWC2_DEPCTL_DPID) { in dwc2_backup_registers()
886 backup->diepctl[i] |= USB_DWC2_DEPCTL_SETD1PID; in dwc2_backup_registers()
888 backup->diepctl[i] |= USB_DWC2_DEPCTL_SETD0PID; in dwc2_backup_registers()
890 backup->dieptsiz[i] = sys_read32((mem_addr_t)&base->in_ep[i].dieptsiz); in dwc2_backup_registers()
891 backup->diepdma[i] = sys_read32((mem_addr_t)&base->in_ep[i].diepdma); in dwc2_backup_registers()
895 backup->doepctl[i] = sys_read32((mem_addr_t)&base->out_ep[i].doepctl); in dwc2_backup_registers()
896 if (backup->doepctl[i] & USB_DWC2_DEPCTL_DPID) { in dwc2_backup_registers()
897 backup->doepctl[i] |= USB_DWC2_DEPCTL_SETD1PID; in dwc2_backup_registers()
899 backup->doepctl[i] |= USB_DWC2_DEPCTL_SETD0PID; in dwc2_backup_registers()
901 backup->doeptsiz[i] = sys_read32((mem_addr_t)&base->out_ep[i].doeptsiz); in dwc2_backup_registers()
902 backup->doepdma[i] = sys_read32((mem_addr_t)&base->out_ep[i].doepdma); in dwc2_backup_registers()
906 backup->pcgcctl = sys_read32((mem_addr_t)&base->pcgcctl); in dwc2_backup_registers()
912 const struct udc_dwc2_config *const config = dev->config; in dwc2_restore_essential_registers()
913 struct usb_dwc2_reg *const base = config->base; in dwc2_restore_essential_registers()
915 struct dwc2_reg_backup *backup = &priv->backup; in dwc2_restore_essential_registers()
916 uint32_t pcgcctl = backup->pcgcctl & USB_DWC2_PCGCCTL_RESTOREVALUE_MASK; in dwc2_restore_essential_registers()
918 sys_write32(backup->glpmcfg, (mem_addr_t)&base->glpmcfg); in dwc2_restore_essential_registers()
919 sys_write32(backup->gi2cctl, (mem_addr_t)&base->gi2cctl); in dwc2_restore_essential_registers()
920 sys_write32(pcgcctl, (mem_addr_t)&base->pcgcctl); in dwc2_restore_essential_registers()
922 sys_write32(backup->gahbcfg | USB_DWC2_GAHBCFG_GLBINTRMASK, in dwc2_restore_essential_registers()
923 (mem_addr_t)&base->gahbcfg); in dwc2_restore_essential_registers()
925 sys_write32(0xFFFFFFFFUL, (mem_addr_t)&base->gintsts); in dwc2_restore_essential_registers()
926 sys_write32(USB_DWC2_GINTSTS_RSTRDONEINT, (mem_addr_t)&base->gintmsk); in dwc2_restore_essential_registers()
928 sys_write32(backup->gusbcfg, (mem_addr_t)&base->gusbcfg); in dwc2_restore_essential_registers()
929 sys_write32(backup->dcfg, (mem_addr_t)&base->dcfg); in dwc2_restore_essential_registers()
932 sys_write32(backup->dcfg, (mem_addr_t)&base->dcfg); in dwc2_restore_essential_registers()
938 sys_write32(pcgcctl, (mem_addr_t)&base->pcgcctl); in dwc2_restore_essential_registers()
942 sys_write32(pcgcctl, (mem_addr_t)&base->pcgcctl); in dwc2_restore_essential_registers()
947 const struct udc_dwc2_config *const config = dev->config; in dwc2_restore_device_registers()
948 struct usb_dwc2_reg *const base = config->base; in dwc2_restore_device_registers()
950 struct dwc2_reg_backup *backup = &priv->backup; in dwc2_restore_device_registers()
952 sys_write32(backup->gotgctl, (mem_addr_t)&base->gotgctl); in dwc2_restore_device_registers()
953 sys_write32(backup->gahbcfg, (mem_addr_t)&base->gahbcfg); in dwc2_restore_device_registers()
954 sys_write32(backup->gusbcfg, (mem_addr_t)&base->gusbcfg); in dwc2_restore_device_registers()
955 sys_write32(backup->gintmsk, (mem_addr_t)&base->gintmsk); in dwc2_restore_device_registers()
956 sys_write32(backup->grxfsiz, (mem_addr_t)&base->grxfsiz); in dwc2_restore_device_registers()
957 sys_write32(backup->gnptxfsiz, (mem_addr_t)&base->gnptxfsiz); in dwc2_restore_device_registers()
958 sys_write32(backup->gdfifocfg, (mem_addr_t)&base->gdfifocfg); in dwc2_restore_device_registers()
960 for (uint8_t i = 1U; i < priv->ineps; i++) { in dwc2_restore_device_registers()
961 sys_write32(backup->dieptxf[i - 1], (mem_addr_t)&base->dieptxf[i - 1]); in dwc2_restore_device_registers()
965 sys_write32(backup->dctl, (mem_addr_t)&base->dctl); in dwc2_restore_device_registers()
968 sys_write32(backup->diepmsk, (mem_addr_t)&base->diepmsk); in dwc2_restore_device_registers()
969 sys_write32(backup->doepmsk, (mem_addr_t)&base->doepmsk); in dwc2_restore_device_registers()
970 sys_write32(backup->daintmsk, (mem_addr_t)&base->daintmsk); in dwc2_restore_device_registers()
973 uint32_t epdir = usb_dwc2_get_ghwcfg1_epdir(priv->ghwcfg1, i); in dwc2_restore_device_registers()
976 sys_write32(backup->dieptsiz[i], (mem_addr_t)&base->in_ep[i].dieptsiz); in dwc2_restore_device_registers()
977 sys_write32(backup->diepdma[i], (mem_addr_t)&base->in_ep[i].diepdma); in dwc2_restore_device_registers()
978 sys_write32(backup->diepctl[i], (mem_addr_t)&base->in_ep[i].diepctl); in dwc2_restore_device_registers()
982 sys_write32(backup->doeptsiz[i], (mem_addr_t)&base->out_ep[i].doeptsiz); in dwc2_restore_device_registers()
983 sys_write32(backup->doepdma[i], (mem_addr_t)&base->out_ep[i].doepdma); in dwc2_restore_device_registers()
984 sys_write32(backup->doepctl[i], (mem_addr_t)&base->out_ep[i].doepctl); in dwc2_restore_device_registers()
991 const struct udc_dwc2_config *const config = dev->config; in dwc2_enter_hibernation()
992 struct usb_dwc2_reg *const base = config->base; in dwc2_enter_hibernation()
994 mem_addr_t gpwrdn_reg = (mem_addr_t)&base->gpwrdn; in dwc2_enter_hibernation()
995 mem_addr_t pcgcctl_reg = (mem_addr_t)&base->pcgcctl; in dwc2_enter_hibernation()
1032 priv->hibernated = 1; in dwc2_enter_hibernation()
1039 const struct udc_dwc2_config *const config = dev->config; in dwc2_exit_hibernation()
1040 struct usb_dwc2_reg *const base = config->base; in dwc2_exit_hibernation()
1042 mem_addr_t gpwrdn_reg = (mem_addr_t)&base->gpwrdn; in dwc2_exit_hibernation()
1043 mem_addr_t pcgcctl_reg = (mem_addr_t)&base->pcgcctl; in dwc2_exit_hibernation()
1063 if (priv->syncrst) { in dwc2_exit_hibernation()
1082 dwc2_wait_for_bit(dev, (mem_addr_t)&base->gintsts, USB_DWC2_GINTSTS_RSTRDONEINT); in dwc2_exit_hibernation()
1084 sys_write32(0xFFFFFFFFUL, (mem_addr_t)&base->gintsts); in dwc2_exit_hibernation()
1097 sys_write32(priv->backup.gusbcfg, (mem_addr_t)&base->gusbcfg); in dwc2_exit_hibernation()
1098 sys_write32(priv->backup.dcfg, (mem_addr_t)&base->dcfg); in dwc2_exit_hibernation()
1099 sys_write32(priv->backup.dctl, (mem_addr_t)&base->dctl); in dwc2_exit_hibernation()
1105 sys_set_bits((mem_addr_t)&base->dctl, USB_DWC2_DCTL_PWRONPRGDONE); in dwc2_exit_hibernation()
1108 sys_write32(USB_DWC2_DCTL_RMTWKUPSIG | priv->backup.dctl, in dwc2_exit_hibernation()
1109 (mem_addr_t)&base->dctl); in dwc2_exit_hibernation()
1113 sys_write32(0xFFFFFFFFUL, (mem_addr_t)&base->gintsts); in dwc2_exit_hibernation()
1118 k_event_clear(&priv->drv_evt, BIT(DWC2_DRV_EVT_ENTER_HIBERNATION)); in cancel_hibernation_request()
1123 if (priv->suspend_type == DWC2_SUSPEND_HIBERNATION) { in request_hibernation()
1124 k_event_post(&priv->drv_evt, BIT(DWC2_DRV_EVT_ENTER_HIBERNATION)); in request_hibernation()
1133 for (uint8_t i = priv->ineps - 1U; i > 0; i--) { in dwc2_unset_unused_fifo()
1136 if (tmp->stat.enabled && (priv->txf_set & BIT(i))) { in dwc2_unset_unused_fifo()
1140 if (!tmp->stat.enabled && (priv->txf_set & BIT(i))) { in dwc2_unset_unused_fifo()
1141 priv->txf_set &= ~BIT(i); in dwc2_unset_unused_fifo()
1147 * In dedicated FIFO mode there are i (i = 1 ... ineps - 1) FIFO size registers,
1156 uint8_t ep_idx = USB_EP_GET_IDX(cfg->addr); in dwc2_set_dedicated_fifo()
1157 const uint32_t addnl = USB_MPS_ADDITIONAL_TRANSACTIONS(cfg->mps); in dwc2_set_dedicated_fifo()
1167 if (priv->bufferdma) { in dwc2_set_dedicated_fifo()
1174 if (priv->dynfifosizing) { in dwc2_set_dedicated_fifo()
1175 if (priv->txf_set & ~BIT_MASK(ep_idx)) { in dwc2_set_dedicated_fifo()
1179 if (priv->txf_set & ~BIT_MASK(ep_idx)) { in dwc2_set_dedicated_fifo()
1181 ep_idx, priv->txf_set & ~BIT_MASK(ep_idx)); in dwc2_set_dedicated_fifo()
1182 return -EIO; in dwc2_set_dedicated_fifo()
1185 if ((ep_idx - 1) != 0U) { in dwc2_set_dedicated_fifo()
1186 txfaddr = dwc2_get_txfdep(dev, ep_idx - 2) + in dwc2_set_dedicated_fifo()
1187 dwc2_get_txfaddr(dev, ep_idx - 2); in dwc2_set_dedicated_fifo()
1189 txfaddr = priv->rxfifo_depth + in dwc2_set_dedicated_fifo()
1190 MIN(UDC_DWC2_FIFO0_DEPTH, priv->max_txfifo_depth[0]); in dwc2_set_dedicated_fifo()
1195 if (txfdep > priv->max_txfifo_depth[ep_idx]) { in dwc2_set_dedicated_fifo()
1196 return -ENOMEM; in dwc2_set_dedicated_fifo()
1200 if (txfaddr + txfdep > priv->dfifodepth) { in dwc2_set_dedicated_fifo()
1201 return -ENOMEM; in dwc2_set_dedicated_fifo()
1204 /* Set FIFO depth (32-bit words) and address */ in dwc2_set_dedicated_fifo()
1205 dwc2_set_txf(dev, ep_idx - 1, txfdep, txfaddr); in dwc2_set_dedicated_fifo()
1207 txfdep = dwc2_get_txfdep(dev, ep_idx - 1); in dwc2_set_dedicated_fifo()
1208 txfaddr = dwc2_get_txfaddr(dev, ep_idx - 1); in dwc2_set_dedicated_fifo()
1211 return -ENOMEM; in dwc2_set_dedicated_fifo()
1219 priv->txf_set |= BIT(ep_idx); in dwc2_set_dedicated_fifo()
1223 ep_idx, cfg->addr, txfaddr, txfdep, dwc2_ftx_avail(dev, ep_idx)); in dwc2_set_dedicated_fifo()
1234 dxepctl0_reg = dwc2_get_dxepctl_reg(dev, cfg->addr); in dwc2_ep_control_enable()
1238 switch (cfg->mps) { in dwc2_ep_control_enable()
1252 return -EINVAL; in dwc2_ep_control_enable()
1257 if (cfg->addr == USB_CONTROL_EP_OUT) { in dwc2_ep_control_enable()
1280 uint8_t ep_idx = USB_EP_GET_IDX(cfg->addr); in udc_dwc2_ep_activate()
1284 LOG_DBG("Enable ep 0x%02x", cfg->addr); in udc_dwc2_ep_activate()
1290 if (USB_EP_DIR_IS_OUT(cfg->addr)) { in udc_dwc2_ep_activate()
1292 dxepctl_reg = (mem_addr_t)&base->out_ep[ep_idx].doepctl; in udc_dwc2_ep_activate()
1294 if (priv->ineps > 0U && ep_idx > (priv->ineps - 1U)) { in udc_dwc2_ep_activate()
1295 LOG_ERR("No resources available for ep 0x%02x", cfg->addr); in udc_dwc2_ep_activate()
1296 return -EINVAL; in udc_dwc2_ep_activate()
1299 dxepctl_reg = (mem_addr_t)&base->in_ep[ep_idx].diepctl; in udc_dwc2_ep_activate()
1310 switch (cfg->attributes & USB_EP_TRANSFER_TYPE_MASK) { in udc_dwc2_ep_activate()
1326 return -EINVAL; in udc_dwc2_ep_activate()
1329 if (USB_EP_DIR_IS_IN(cfg->addr) && udc_mps_ep_size(cfg) != 0U) { in udc_dwc2_ep_activate()
1343 for (uint8_t i = 1U; i < priv->ineps; i++) { in udc_dwc2_ep_activate()
1345 i, sys_read32((mem_addr_t)&base->dieptxf[i - 1U]), i, dxepctl); in udc_dwc2_ep_activate()
1356 uint8_t ep_idx = USB_EP_GET_IDX(cfg->addr); in dwc2_unset_dedicated_fifo()
1361 if (priv->dynfifosizing) { in dwc2_unset_dedicated_fifo()
1362 if (priv->txf_set & ~BIT_MASK(ep_idx)) { in dwc2_unset_dedicated_fifo()
1364 ep_idx, priv->txf_set & ~BIT_MASK(ep_idx)); in dwc2_unset_dedicated_fifo()
1368 dwc2_set_txf(dev, ep_idx - 1, 0, 0); in dwc2_unset_dedicated_fifo()
1371 priv->txf_set &= ~BIT(ep_idx); in dwc2_unset_dedicated_fifo()
1387 uint8_t ep_idx = USB_EP_GET_IDX(cfg->addr); in udc_dwc2_ep_disable()
1392 dxepctl_reg = dwc2_get_dxepctl_reg(dev, cfg->addr); in udc_dwc2_ep_disable()
1413 * does and then it'll "double"-finish when it actually finishes) in udc_dwc2_ep_disable()
1418 if (USB_EP_DIR_IS_OUT(cfg->addr)) { in udc_dwc2_ep_disable()
1422 dctl_reg = (mem_addr_t)&base->dctl; in udc_dwc2_ep_disable()
1423 gintsts_reg = (mem_addr_t)&base->gintsts; in udc_dwc2_ep_disable()
1424 doepint_reg = (mem_addr_t)&base->out_ep[ep_idx].doepint; in udc_dwc2_ep_disable()
1463 diepint_reg = (mem_addr_t)&base->in_ep[ep_idx].diepint; in udc_dwc2_ep_disable()
1490 udc_ep_set_busy(dev, cfg->addr, false); in udc_dwc2_ep_disable()
1494 * tries to access the endpoint.
1499 uint8_t ep_idx = USB_EP_GET_IDX(cfg->addr); in udc_dwc2_ep_deactivate()
1503 dxepctl_reg = dwc2_get_dxepctl_reg(dev, cfg->addr); in udc_dwc2_ep_deactivate()
1508 cfg->addr, ep_idx, dxepctl); in udc_dwc2_ep_deactivate()
1516 cfg->addr, ep_idx, dxepctl); in udc_dwc2_ep_deactivate()
1519 if (USB_EP_DIR_IS_IN(cfg->addr) && udc_mps_ep_size(cfg) != 0U && in udc_dwc2_ep_deactivate()
1527 if (cfg->addr == USB_CONTROL_EP_OUT) { in udc_dwc2_ep_deactivate()
1528 struct net_buf *buf = udc_buf_get_all(dev, cfg->addr); in udc_dwc2_ep_deactivate()
1542 uint8_t ep_idx = USB_EP_GET_IDX(cfg->addr); in udc_dwc2_ep_set_halt()
1546 LOG_DBG("Set halt ep 0x%02x", cfg->addr); in udc_dwc2_ep_set_halt()
1548 cfg->stat.halted = true; in udc_dwc2_ep_set_halt()
1558 mem_addr_t dxepctl_reg = dwc2_get_dxepctl_reg(dev, cfg->addr); in udc_dwc2_ep_clear_halt()
1566 LOG_DBG("Clear halt ep 0x%02x", cfg->addr); in udc_dwc2_ep_clear_halt()
1567 cfg->stat.halted = false; in udc_dwc2_ep_clear_halt()
1570 if (udc_buf_peek(dev, cfg->addr)) { in udc_dwc2_ep_clear_halt()
1573 if (USB_EP_DIR_IS_IN(cfg->addr)) { in udc_dwc2_ep_clear_halt()
1574 ep_bit = BIT(USB_EP_GET_IDX(cfg->addr)); in udc_dwc2_ep_clear_halt()
1576 ep_bit = BIT(16 + USB_EP_GET_IDX(cfg->addr)); in udc_dwc2_ep_clear_halt()
1579 k_event_post(&priv->xfer_new, ep_bit); in udc_dwc2_ep_clear_halt()
1580 k_event_post(&priv->drv_evt, BIT(DWC2_DRV_EVT_XFER)); in udc_dwc2_ep_clear_halt()
1592 LOG_DBG("%p enqueue %x %p", dev, cfg->addr, buf); in udc_dwc2_ep_enqueue()
1595 if (!cfg->stat.halted) { in udc_dwc2_ep_enqueue()
1598 if (USB_EP_DIR_IS_IN(cfg->addr)) { in udc_dwc2_ep_enqueue()
1599 ep_bit = BIT(USB_EP_GET_IDX(cfg->addr)); in udc_dwc2_ep_enqueue()
1601 ep_bit = BIT(16 + USB_EP_GET_IDX(cfg->addr)); in udc_dwc2_ep_enqueue()
1604 k_event_post(&priv->xfer_new, ep_bit); in udc_dwc2_ep_enqueue()
1605 k_event_post(&priv->drv_evt, BIT(DWC2_DRV_EVT_XFER)); in udc_dwc2_ep_enqueue()
1618 buf = udc_buf_get_all(dev, cfg->addr); in udc_dwc2_ep_dequeue()
1620 udc_submit_ep_event(dev, buf, -ECONNABORTED); in udc_dwc2_ep_dequeue()
1623 udc_ep_set_busy(dev, cfg->addr, false); in udc_dwc2_ep_dequeue()
1625 LOG_DBG("dequeue ep 0x%02x", cfg->addr); in udc_dwc2_ep_dequeue()
1633 mem_addr_t dcfg_reg = (mem_addr_t)&base->dcfg; in udc_dwc2_set_address()
1637 return -EINVAL; in udc_dwc2_set_address()
1653 mem_addr_t dctl_reg = (mem_addr_t)&base->dctl; in udc_dwc2_test_mode()
1657 return -EINVAL; in udc_dwc2_test_mode()
1662 return -EALREADY; in udc_dwc2_test_mode()
1683 k_event_post(&priv->drv_evt, BIT(DWC2_DRV_EVT_REMOTE_WAKEUP)); in udc_dwc2_host_wakeup()
1693 switch (priv->enumspd) { in udc_dwc2_device_speed()
1711 mem_addr_t grstctl_reg = (mem_addr_t)&base->grstctl; in dwc2_core_soft_reset()
1715 /* Check AHB master idle state */ in dwc2_core_soft_reset()
1722 return -EIO; in dwc2_core_soft_reset()
1734 return -EIO; in dwc2_core_soft_reset()
1748 const struct udc_dwc2_config *const config = dev->config; in udc_dwc2_init_controller()
1750 struct usb_dwc2_reg *const base = config->base; in udc_dwc2_init_controller()
1751 mem_addr_t grxfsiz_reg = (mem_addr_t)&base->grxfsiz; in udc_dwc2_init_controller()
1752 mem_addr_t gahbcfg_reg = (mem_addr_t)&base->gahbcfg; in udc_dwc2_init_controller()
1753 mem_addr_t gusbcfg_reg = (mem_addr_t)&base->gusbcfg; in udc_dwc2_init_controller()
1754 mem_addr_t dcfg_reg = (mem_addr_t)&base->dcfg; in udc_dwc2_init_controller()
1770 priv->ghwcfg1 = sys_read32((mem_addr_t)&base->ghwcfg1); in udc_dwc2_init_controller()
1771 ghwcfg2 = sys_read32((mem_addr_t)&base->ghwcfg2); in udc_dwc2_init_controller()
1772 ghwcfg3 = sys_read32((mem_addr_t)&base->ghwcfg3); in udc_dwc2_init_controller()
1773 ghwcfg4 = sys_read32((mem_addr_t)&base->ghwcfg4); in udc_dwc2_init_controller()
1777 return -ENOTSUP; in udc_dwc2_init_controller()
1791 priv->bufferdma = (usb_dwc2_get_ghwcfg2_otgarch(ghwcfg2) == in udc_dwc2_init_controller()
1795 priv->bufferdma = 0; in udc_dwc2_init_controller()
1796 } else if (priv->bufferdma) { in udc_dwc2_init_controller()
1802 priv->dynfifosizing = true; in udc_dwc2_init_controller()
1808 priv->suspend_type = DWC2_SUSPEND_HIBERNATION; in udc_dwc2_init_controller()
1810 priv->suspend_type = DWC2_SUSPEND_NO_POWER_SAVING; in udc_dwc2_init_controller()
1814 priv->numdeveps = usb_dwc2_get_ghwcfg2_numdeveps(ghwcfg2) + 1U; in udc_dwc2_init_controller()
1815 priv->ineps = usb_dwc2_get_ghwcfg4_ineps(ghwcfg4) + 1U; in udc_dwc2_init_controller()
1816 LOG_DBG("Number of endpoints (NUMDEVEPS + 1) %u", priv->numdeveps); in udc_dwc2_init_controller()
1817 LOG_DBG("Number of IN endpoints (INEPS + 1) %u", priv->ineps); in udc_dwc2_init_controller()
1828 priv->dfifodepth = usb_dwc2_get_ghwcfg3_dfifodepth(ghwcfg3); in udc_dwc2_init_controller()
1829 LOG_DBG("DFIFO depth (DFIFODEPTH) %u bytes", priv->dfifodepth * 4); in udc_dwc2_init_controller()
1831 priv->max_pktcnt = GHWCFG3_PKTCOUNT(usb_dwc2_get_ghwcfg3_pktsizewidth(ghwcfg3)); in udc_dwc2_init_controller()
1832 priv->max_xfersize = GHWCFG3_XFERSIZE(usb_dwc2_get_ghwcfg3_xfersizewidth(ghwcfg3)); in udc_dwc2_init_controller()
1834 priv->max_pktcnt, priv->max_xfersize); in udc_dwc2_init_controller()
1848 priv->syncrst = 1; in udc_dwc2_init_controller()
1854 if (priv->bufferdma) { in udc_dwc2_init_controller()
1906 priv->outeps = 0U; in udc_dwc2_init_controller()
1907 for (uint8_t i = 0U; i < priv->numdeveps; i++) { in udc_dwc2_init_controller()
1908 uint32_t epdir = usb_dwc2_get_ghwcfg1_epdir(priv->ghwcfg1, i); in udc_dwc2_init_controller()
1915 priv->outeps++; in udc_dwc2_init_controller()
1919 LOG_DBG("Number of OUT endpoints %u", priv->outeps); in udc_dwc2_init_controller()
1922 * not exceed the power-on values. in udc_dwc2_init_controller()
1924 val = sys_read32((mem_addr_t)&base->gnptxfsiz); in udc_dwc2_init_controller()
1925 priv->max_txfifo_depth[0] = usb_dwc2_get_gnptxfsiz_nptxfdep(val); in udc_dwc2_init_controller()
1926 for (uint8_t i = 1; i < priv->ineps; i++) { in udc_dwc2_init_controller()
1927 priv->max_txfifo_depth[i] = dwc2_get_txfdep(dev, i - 1); in udc_dwc2_init_controller()
1930 priv->rxfifo_depth = usb_dwc2_get_grxfsiz(sys_read32(grxfsiz_reg)); in udc_dwc2_init_controller()
1932 if (priv->dynfifosizing) { in udc_dwc2_init_controller()
1949 default_depth += priv->outeps * 2U; in udc_dwc2_init_controller()
1955 priv->rxfifo_depth = MIN(priv->rxfifo_depth, default_depth); in udc_dwc2_init_controller()
1956 sys_write32(usb_dwc2_set_grxfsiz(priv->rxfifo_depth), grxfsiz_reg); in udc_dwc2_init_controller()
1959 val = MIN(UDC_DWC2_FIFO0_DEPTH, priv->max_txfifo_depth[0]); in udc_dwc2_init_controller()
1961 usb_dwc2_set_gnptxfsiz_nptxfstaddr(priv->rxfifo_depth); in udc_dwc2_init_controller()
1963 sys_write32(gnptxfsiz, (mem_addr_t)&base->gnptxfsiz); in udc_dwc2_init_controller()
1966 LOG_DBG("RX FIFO size %u bytes", priv->rxfifo_depth * 4); in udc_dwc2_init_controller()
1967 for (uint8_t i = 1U; i < priv->ineps; i++) { in udc_dwc2_init_controller()
1969 i, priv->max_txfifo_depth[i], dwc2_get_txfaddr(dev, i)); in udc_dwc2_init_controller()
1975 return -EIO; in udc_dwc2_init_controller()
1981 return -EIO; in udc_dwc2_init_controller()
1990 (mem_addr_t)&base->gintmsk); in udc_dwc2_init_controller()
1997 const struct udc_dwc2_config *const config = dev->config; in udc_dwc2_enable()
2019 sys_set_bits((mem_addr_t)&base->gahbcfg, USB_DWC2_GAHBCFG_GLBINTRMASK); in udc_dwc2_enable()
2020 config->irq_enable_func(dev); in udc_dwc2_enable()
2023 sys_clear_bits((mem_addr_t)&base->dctl, USB_DWC2_DCTL_SFTDISCON); in udc_dwc2_enable()
2031 const struct udc_dwc2_config *const config = dev->config; in udc_dwc2_disable()
2034 mem_addr_t dctl_reg = (mem_addr_t)&base->dctl; in udc_dwc2_disable()
2043 return -EIO; in udc_dwc2_disable()
2048 return -EIO; in udc_dwc2_disable()
2051 config->irq_disable_func(dev); in udc_dwc2_disable()
2053 if (priv->hibernated) { in udc_dwc2_disable()
2055 priv->hibernated = 0; in udc_dwc2_disable()
2058 sys_clear_bits((mem_addr_t)&base->gahbcfg, USB_DWC2_GAHBCFG_GLBINTRMASK); in udc_dwc2_disable()
2097 const struct udc_dwc2_config *config = dev->config; in dwc2_driver_preinit()
2099 struct udc_data *data = dev->data; in dwc2_driver_preinit()
2105 k_mutex_init(&data->mutex); in dwc2_driver_preinit()
2107 k_event_init(&priv->drv_evt); in dwc2_driver_preinit()
2108 k_event_init(&priv->xfer_new); in dwc2_driver_preinit()
2109 k_event_init(&priv->xfer_finished); in dwc2_driver_preinit()
2111 data->caps.rwup = true; in dwc2_driver_preinit()
2112 data->caps.addr_before_status = true; in dwc2_driver_preinit()
2113 data->caps.mps0 = UDC_MPS0_64; in dwc2_driver_preinit()
2116 if (data->caps.hs) { in dwc2_driver_preinit()
2121 * At this point, we cannot or do not want to access the hardware in dwc2_driver_preinit()
2128 ineps = usb_dwc2_get_ghwcfg4_ineps(config->ghwcfg4) + 1U; in dwc2_driver_preinit()
2129 numdeveps = usb_dwc2_get_ghwcfg2_numdeveps(config->ghwcfg2) + 1U; in dwc2_driver_preinit()
2134 uint32_t epdir = usb_dwc2_get_ghwcfg1_epdir(config->ghwcfg1, i); in dwc2_driver_preinit()
2142 config->ep_cfg_out[n].caps.control = 1; in dwc2_driver_preinit()
2143 config->ep_cfg_out[n].caps.mps = 64; in dwc2_driver_preinit()
2145 config->ep_cfg_out[n].caps.bulk = 1; in dwc2_driver_preinit()
2146 config->ep_cfg_out[n].caps.interrupt = 1; in dwc2_driver_preinit()
2147 config->ep_cfg_out[n].caps.iso = 1; in dwc2_driver_preinit()
2148 config->ep_cfg_out[n].caps.high_bandwidth = data->caps.hs; in dwc2_driver_preinit()
2149 config->ep_cfg_out[n].caps.mps = mps; in dwc2_driver_preinit()
2152 config->ep_cfg_out[n].caps.out = 1; in dwc2_driver_preinit()
2153 config->ep_cfg_out[n].addr = USB_EP_DIR_OUT | i; in dwc2_driver_preinit()
2156 err = udc_register_ep(dev, &config->ep_cfg_out[n]); in dwc2_driver_preinit()
2164 if (n >= config->num_out_eps) { in dwc2_driver_preinit()
2170 uint32_t epdir = usb_dwc2_get_ghwcfg1_epdir(config->ghwcfg1, i); in dwc2_driver_preinit()
2178 config->ep_cfg_in[n].caps.control = 1; in dwc2_driver_preinit()
2179 config->ep_cfg_in[n].caps.mps = 64; in dwc2_driver_preinit()
2181 config->ep_cfg_in[n].caps.bulk = 1; in dwc2_driver_preinit()
2182 config->ep_cfg_in[n].caps.interrupt = 1; in dwc2_driver_preinit()
2183 config->ep_cfg_in[n].caps.iso = 1; in dwc2_driver_preinit()
2184 config->ep_cfg_in[n].caps.high_bandwidth = data->caps.hs; in dwc2_driver_preinit()
2185 config->ep_cfg_in[n].caps.mps = mps; in dwc2_driver_preinit()
2188 config->ep_cfg_in[n].caps.in = 1; in dwc2_driver_preinit()
2189 config->ep_cfg_in[n].addr = USB_EP_DIR_IN | i; in dwc2_driver_preinit()
2192 err = udc_register_ep(dev, &config->ep_cfg_in[n]); in dwc2_driver_preinit()
2200 if (n >= MIN(ineps, config->num_in_eps)) { in dwc2_driver_preinit()
2205 config->make_thread(dev); in dwc2_driver_preinit()
2227 for (uint8_t i = 0U; i < priv->numdeveps; i++) { in dwc2_on_bus_reset()
2228 uint32_t epdir = usb_dwc2_get_ghwcfg1_epdir(priv->ghwcfg1, i); in dwc2_on_bus_reset()
2240 if (priv->bufferdma) { in dwc2_on_bus_reset()
2244 sys_write32(doepmsk, (mem_addr_t)&base->doepmsk); in dwc2_on_bus_reset()
2245 sys_set_bits((mem_addr_t)&base->diepmsk, USB_DWC2_DIEPINT_XFERCOMPL); in dwc2_on_bus_reset()
2248 if (!priv->bufferdma) { in dwc2_on_bus_reset()
2249 sys_set_bits((mem_addr_t)&base->gintmsk, in dwc2_on_bus_reset()
2254 sys_clear_bits((mem_addr_t)&base->dcfg, USB_DWC2_DCFG_DEVADDR_MASK); in dwc2_on_bus_reset()
2257 priv->enumdone = 0; in dwc2_on_bus_reset()
2266 dsts = sys_read32((mem_addr_t)&base->dsts); in dwc2_handle_enumdone()
2267 priv->enumspd = usb_dwc2_get_dsts_enumspd(dsts); in dwc2_handle_enumdone()
2268 priv->enumdone = 1; in dwc2_handle_enumdone()
2278 /* FIFO access is always in 32-bit words */ in dwc2_read_fifo_setup()
2288 * bottom-half processing because the events arrive in a queue and in dwc2_read_fifo_setup()
2293 &priv->setup[offset]); in dwc2_read_fifo_setup()
2315 grxstsp = sys_read32((mem_addr_t)&base->grxstsp); in dwc2_handle_rxflvl()
2329 buf = udc_buf_peek(dev, ep_cfg->addr); in dwc2_handle_rxflvl()
2355 buf = udc_buf_peek(dev, ep_cfg->addr); in dwc2_handle_in_xfercompl()
2357 udc_submit_event(dev, UDC_EVT_ERROR, -ENOBUFS); in dwc2_handle_in_xfercompl()
2361 net_buf_pull(buf, priv->tx_len[ep_idx]); in dwc2_handle_in_xfercompl()
2362 if (buf->len && dwc2_tx_fifo_write(dev, ep_cfg, buf) == 0) { in dwc2_handle_in_xfercompl()
2366 k_event_post(&priv->xfer_finished, BIT(ep_idx)); in dwc2_handle_in_xfercompl()
2367 k_event_post(&priv->drv_evt, BIT(DWC2_DRV_EVT_EP_FINISHED)); in dwc2_handle_in_xfercompl()
2377 diepmsk = sys_read32((mem_addr_t)&base->diepmsk); in dwc2_handle_iepint()
2378 daint = sys_read32((mem_addr_t)&base->daint); in dwc2_handle_iepint()
2381 mem_addr_t diepint_reg = (mem_addr_t)&base->in_ep[n].diepint; in dwc2_handle_iepint()
2402 sys_write32(USB_DWC2_GINTSTS_IEPINT, (mem_addr_t)&base->gintsts); in dwc2_handle_iepint()
2416 doeptsiz = sys_read32((mem_addr_t)&base->out_ep[ep_idx].doeptsiz); in dwc2_handle_out_xfercompl()
2418 buf = udc_buf_peek(dev, ep_cfg->addr); in dwc2_handle_out_xfercompl()
2420 LOG_ERR("No buffer for ep 0x%02x", ep_cfg->addr); in dwc2_handle_out_xfercompl()
2421 udc_submit_event(dev, UDC_EVT_ERROR, -ENOBUFS); in dwc2_handle_out_xfercompl()
2428 bcnt = usb_dwc2_get_doeptsizn_xfersize(priv->rx_siz[ep_idx]) - in dwc2_handle_out_xfercompl()
2435 pkts = usb_dwc2_get_doeptsizn_pktcnt(priv->rx_siz[ep_idx]) - in dwc2_handle_out_xfercompl()
2454 if (!priv->bufferdma) { in dwc2_handle_out_xfercompl()
2463 if (priv->bufferdma && bcnt) { in dwc2_handle_out_xfercompl()
2464 sys_cache_data_invd_range(buf->data, bcnt); in dwc2_handle_out_xfercompl()
2472 k_event_post(&priv->xfer_finished, BIT(16 + ep_idx)); in dwc2_handle_out_xfercompl()
2473 k_event_post(&priv->drv_evt, BIT(DWC2_DRV_EVT_EP_FINISHED)); in dwc2_handle_out_xfercompl()
2485 doepmsk = sys_read32((mem_addr_t)&base->doepmsk); in dwc2_handle_oepint()
2486 daint = sys_read32((mem_addr_t)&base->daint); in dwc2_handle_oepint()
2489 mem_addr_t doepint_reg = (mem_addr_t)&base->out_ep[n].doepint; in dwc2_handle_oepint()
2507 if (priv->bufferdma && (status & USB_DWC2_DOEPINT_XFERCOMPL) && in dwc2_handle_oepint()
2519 addr = sys_read32((mem_addr_t)&base->out_ep[0].doepdma); in dwc2_handle_oepint()
2520 sys_cache_data_invd_range((void *)(addr - 8), 8); in dwc2_handle_oepint()
2521 memcpy(priv->setup, (void *)(addr - 8), sizeof(priv->setup)); in dwc2_handle_oepint()
2525 k_event_post(&priv->drv_evt, BIT(DWC2_DRV_EVT_SETUP)); in dwc2_handle_oepint()
2544 sys_write32(USB_DWC2_GINTSTS_OEPINT, (mem_addr_t)&base->gintsts); in dwc2_handle_oepint()
2553 const struct udc_dwc2_config *const config = dev->config; in dwc2_handle_incompisoin()
2554 struct usb_dwc2_reg *const base = config->base; in dwc2_handle_incompisoin()
2556 mem_addr_t gintsts_reg = (mem_addr_t)&base->gintsts; in dwc2_handle_incompisoin()
2557 const uint32_t mask = in dwc2_handle_incompisoin() local
2565 for (uint8_t i = 1U; i < priv->numdeveps; i++) { in dwc2_handle_incompisoin()
2566 uint32_t epdir = usb_dwc2_get_ghwcfg1_epdir(priv->ghwcfg1, i); in dwc2_handle_incompisoin()
2576 if ((diepctl & mask) == val) { in dwc2_handle_incompisoin()
2581 __ASSERT_NO_MSG(cfg && cfg->stat.enabled && in dwc2_handle_incompisoin()
2586 buf = udc_buf_get(dev, cfg->addr); in dwc2_handle_incompisoin()
2607 const struct udc_dwc2_config *const config = dev->config; in dwc2_handle_incompisoout()
2608 struct usb_dwc2_reg *const base = config->base; in dwc2_handle_incompisoout()
2610 mem_addr_t gintsts_reg = (mem_addr_t)&base->gintsts; in dwc2_handle_incompisoout()
2611 const uint32_t mask = in dwc2_handle_incompisoout() local
2617 ((priv->sof_num & 1) ? USB_DWC2_DEPCTL_DPID : 0) | in dwc2_handle_incompisoout()
2620 for (uint8_t i = 1U; i < priv->numdeveps; i++) { in dwc2_handle_incompisoout()
2621 uint32_t epdir = usb_dwc2_get_ghwcfg1_epdir(priv->ghwcfg1, i); in dwc2_handle_incompisoout()
2631 if ((doepctl & mask) == val) { in dwc2_handle_incompisoout()
2636 __ASSERT_NO_MSG(cfg && cfg->stat.enabled && in dwc2_handle_incompisoout()
2641 buf = udc_buf_get(dev, cfg->addr); in dwc2_handle_incompisoout()
2654 const struct udc_dwc2_config *const config = dev->config; in udc_dwc2_isr_handler()
2655 struct usb_dwc2_reg *const base = config->base; in udc_dwc2_isr_handler()
2657 mem_addr_t gintsts_reg = (mem_addr_t)&base->gintsts; in udc_dwc2_isr_handler()
2661 if (priv->hibernated) { in udc_dwc2_isr_handler()
2662 uint32_t gpwrdn = sys_read32((mem_addr_t)&base->gpwrdn); in udc_dwc2_isr_handler()
2666 sys_write32(gpwrdn, (mem_addr_t)&base->gpwrdn); in udc_dwc2_isr_handler()
2676 k_event_post(&priv->drv_evt, in udc_dwc2_isr_handler()
2681 k_event_post(&priv->drv_evt, BIT(DWC2_DRV_EVT_HIBERNATION_EXIT_BUS_RESET)); in udc_dwc2_isr_handler()
2688 gintmsk = sys_read32((mem_addr_t)&base->gintmsk); in udc_dwc2_isr_handler()
2701 dsts = sys_read32((mem_addr_t)&base->dsts); in udc_dwc2_isr_handler()
2702 priv->sof_num = usb_dwc2_get_dsts_soffn(dsts); in udc_dwc2_isr_handler()
2737 /* Handle RxFIFO Non-Empty interrupt */ in udc_dwc2_isr_handler()
2778 priv->hibernated = 0; in dwc2_handle_hibernation_exit()
2793 sys_clear_bits((mem_addr_t)&base->dctl, USB_DWC2_DCTL_RMTWKUPSIG); in dwc2_handle_hibernation_exit()
2802 k_event_clear(&priv->xfer_new, UINT32_MAX); in dwc2_handle_hibernation_exit()
2803 k_event_clear(&priv->xfer_finished, UINT32_MAX); in dwc2_handle_hibernation_exit()
2807 if (k_event_test(&priv->xfer_new, UINT32_MAX)) { in dwc2_handle_hibernation_exit()
2808 k_event_post(&priv->drv_evt, BIT(DWC2_DRV_EVT_XFER)); in dwc2_handle_hibernation_exit()
2811 if (k_event_test(&priv->xfer_finished, UINT32_MAX)) { in dwc2_handle_hibernation_exit()
2812 k_event_post(&priv->drv_evt, BIT(DWC2_DRV_EVT_EP_FINISHED)); in dwc2_handle_hibernation_exit()
2823 bit = find_lsb_set(*bitmap) - 1; in pull_next_ep_from_bitmap()
2827 return USB_EP_DIR_OUT | (bit - 16); in pull_next_ep_from_bitmap()
2838 const struct udc_dwc2_config *const config = dev->config; in dwc2_thread_handler()
2847 /* This is the bottom-half of the ISR handler and the place where in dwc2_thread_handler()
2850 evt = k_event_wait(&priv->drv_evt, UINT32_MAX, false, K_FOREVER); in dwc2_thread_handler()
2855 k_event_clear(&priv->drv_evt, BIT(DWC2_DRV_EVT_XFER)); in dwc2_thread_handler()
2857 if (!priv->hibernated) { in dwc2_thread_handler()
2859 eps = k_event_test(&priv->xfer_new, UINT32_MAX); in dwc2_thread_handler()
2860 k_event_clear(&priv->xfer_new, eps); in dwc2_thread_handler()
2870 if (!udc_ep_is_busy(dev, ep_cfg->addr)) { in dwc2_thread_handler()
2873 LOG_DBG("ep 0x%02x busy", ep_cfg->addr); in dwc2_thread_handler()
2879 k_event_clear(&priv->drv_evt, BIT(DWC2_DRV_EVT_EP_FINISHED)); in dwc2_thread_handler()
2881 if (!priv->hibernated) { in dwc2_thread_handler()
2882 eps = k_event_test(&priv->xfer_finished, UINT32_MAX); in dwc2_thread_handler()
2883 k_event_clear(&priv->xfer_finished, eps); in dwc2_thread_handler()
2897 LOG_DBG("DOUT event ep 0x%02x", ep_cfg->addr); in dwc2_thread_handler()
2901 if (!udc_ep_is_busy(dev, ep_cfg->addr)) { in dwc2_thread_handler()
2904 LOG_DBG("ep 0x%02x busy", ep_cfg->addr); in dwc2_thread_handler()
2910 k_event_clear(&priv->drv_evt, BIT(DWC2_DRV_EVT_SETUP)); in dwc2_thread_handler()
2917 k_event_clear(&priv->drv_evt, BIT(DWC2_DRV_EVT_REMOTE_WAKEUP) | in dwc2_thread_handler()
2920 if (priv->hibernated) { in dwc2_thread_handler()
2921 config->irq_disable_func(dev); in dwc2_thread_handler()
2925 config->irq_enable_func(dev); in dwc2_thread_handler()
2927 sys_set_bits((mem_addr_t)&base->dctl, USB_DWC2_DCTL_RMTWKUPSIG); in dwc2_thread_handler()
2935 sys_clear_bits((mem_addr_t)&base->dctl, USB_DWC2_DCTL_RMTWKUPSIG); in dwc2_thread_handler()
2940 config->irq_disable_func(dev); in dwc2_thread_handler()
2942 prev = k_event_clear(&priv->drv_evt, BIT(DWC2_DRV_EVT_ENTER_HIBERNATION)); in dwc2_thread_handler()
2949 config->irq_enable_func(dev); in dwc2_thread_handler()
2956 config->irq_disable_func(dev); in dwc2_thread_handler()
2958 prev = k_event_clear(&priv->drv_evt, hibernation_exit_events); in dwc2_thread_handler()
2961 if (priv->hibernated) { in dwc2_thread_handler()
2965 config->irq_enable_func(dev); in dwc2_thread_handler()
3015 * A UDC driver should always be implemented as a multi-instance
3034 k_thread_create(&priv->thread_data, \
3042 k_thread_name_set(&priv->thread_data, dev->name); \