Lines Matching refs:sys_write32
72 sys_write32(match, TIMER_BASE_ADDR + XTTCPS_MATCH_0_OFFSET); in update_match()
154 sys_write32(XTTCPS_CNT_CNTRL_DIS_MASK, in sys_clock_driver_init()
163 sys_write32(XTTCPS_CNT_CNTRL_RESET_VALUE, in sys_clock_driver_init()
165 sys_write32(0, TIMER_BASE_ADDR + XTTCPS_CLK_CNTRL_OFFSET); in sys_clock_driver_init()
166 sys_write32(0, TIMER_BASE_ADDR + XTTCPS_INTERVAL_VAL_OFFSET); in sys_clock_driver_init()
167 sys_write32(0, TIMER_BASE_ADDR + XTTCPS_MATCH_0_OFFSET); in sys_clock_driver_init()
168 sys_write32(0, TIMER_BASE_ADDR + XTTCPS_MATCH_1_OFFSET); in sys_clock_driver_init()
169 sys_write32(0, TIMER_BASE_ADDR + XTTCPS_MATCH_2_OFFSET); in sys_clock_driver_init()
170 sys_write32(0, TIMER_BASE_ADDR + XTTCPS_IER_OFFSET); in sys_clock_driver_init()
171 sys_write32(XTTCPS_IXR_ALL_MASK, TIMER_BASE_ADDR + XTTCPS_ISR_OFFSET); in sys_clock_driver_init()
176 sys_write32(reg_val, TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET); in sys_clock_driver_init()
181 sys_write32(reg_val, TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET); in sys_clock_driver_init()
186 sys_write32(reg_val, TIMER_BASE_ADDR + XTTCPS_MATCH_0_OFFSET); in sys_clock_driver_init()
195 sys_write32(reg_val, TIMER_BASE_ADDR + XTTCPS_IER_OFFSET); in sys_clock_driver_init()
200 sys_write32(reg_val, TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET); in sys_clock_driver_init()