Lines Matching refs:RTC0
29 #define RTC0 ((RtcMode0 *) DT_INST_REG_ADDR(0)) macro
96 while (RTC0->STATUS.reg & RTC_STATUS_SYNCBUSY) { in rtc_sync()
99 while (RTC0->SYNCBUSY.reg) { in rtc_sync()
112 RTC0->READREQ.reg = RTC_READREQ_RREQ; in rtc_count()
115 return RTC0->COUNT.reg; in rtc_count()
123 RTC0->INTENCLR.reg = RTC_MODE0_INTENCLR_MASK; in rtc_reset()
125 RTC0->INTFLAG.reg = RTC_MODE0_INTFLAG_MASK; in rtc_reset()
129 RTC0->CTRL.reg &= ~RTC_MODE0_CTRL_ENABLE; in rtc_reset()
131 RTC0->CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE; in rtc_reset()
138 RTC0->CTRL.bit.SWRST = 1; in rtc_reset()
139 while (RTC0->CTRL.bit.SWRST) { in rtc_reset()
142 RTC0->CTRLA.bit.SWRST = 1; in rtc_reset()
143 while (RTC0->CTRLA.bit.SWRST) { in rtc_reset()
153 uint16_t status = RTC0->INTFLAG.reg; in rtc_isr()
155 RTC0->INTFLAG.reg = status; in rtc_isr()
206 RTC0->COMP[0].reg = count + timeout; in sys_clock_set_timeout()
297 RTC0->CTRL.reg = ctrl; in sys_clock_driver_init()
299 RTC0->CTRLA.reg = ctrl; in sys_clock_driver_init()
304 RTC0->INTENSET.reg = RTC_MODE0_INTENSET_CMP0; in sys_clock_driver_init()
308 RTC0->COMP[0].reg = CYCLES_PER_TICK; in sys_clock_driver_init()
309 RTC0->INTENSET.reg = RTC_MODE0_INTENSET_OVF; in sys_clock_driver_init()
317 RTC0->CTRL.reg |= RTC_MODE0_CTRL_ENABLE; in sys_clock_driver_init()
319 RTC0->CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE; in sys_clock_driver_init()