Lines Matching +full:nuclei +full:- +full:systimer

3  * Copyright (c) 2018-2023 Intel Corporation
5  * SPDX-License-Identifier: Apache-2.0
75 	/* Per spec, the RISC-V MTIME/MTIMECMP registers are 64 bit,
112 	uint64_t dcycles = now - last_count;
144 		if ((cyc - last_count) > CYCLES_MAX) {
161 	uint64_t dcycles = now - last_count;