Lines Matching refs:sys_write32
69 sys_write32(reg_val, TIMER_BASE_ADDR + CMCSR0_OFFSET); in cmt_isr()
109 sys_write32(CLKEN0 | CLKEN1, TIMER_BASE_ADDR + CMCLKE); in sys_clock_driver_init()
114 sys_write32(reg_val, TIMER_BASE_ADDR + CMSTR0_OFFSET); in sys_clock_driver_init()
118 sys_write32(reg_val, TIMER_BASE_ADDR + CMSTR1_OFFSET); in sys_clock_driver_init()
121 sys_write32(CSR_FREE_RUN | CSR_CLK_DIV_1 | CSR_ENABLE_INTERRUPT, in sys_clock_driver_init()
125 sys_write32(CSR_FREE_RUN | CSR_CLK_DIV_1, in sys_clock_driver_init()
129 sys_write32(CYCLES_PER_TICK, TIMER_BASE_ADDR + CMCOR0_OFFSET); in sys_clock_driver_init()
132 sys_write32(0xffffffff, TIMER_BASE_ADDR + CMCOR1_OFFSET); in sys_clock_driver_init()
138 sys_write32(0, TIMER_BASE_ADDR + CMCNT0_OFFSET); in sys_clock_driver_init()
154 sys_write32(START_BIT, TIMER_BASE_ADDR + CMSTR0_OFFSET); in sys_clock_driver_init()
155 sys_write32(START_BIT, TIMER_BASE_ADDR + CMSTR1_OFFSET); in sys_clock_driver_init()