Lines Matching +full:dummy +full:- +full:bytes +full:- +full:count
4 * SPDX-License-Identifier: Apache-2.0
58 REG8(®s->TX_FIFO) = data8; in txb_wr8()
63 return REG8(®s->RX_FIFO); in rxb_rd8()
87 qmode = regs->MODE & ~(MCHP_QMSPI_M_FDIV_MASK); in qmspi_set_frequency()
89 regs->MODE = qmode; in qmspi_set_frequency()
129 if (((regs->MODE >> MCHP_QMSPI_M_FDIV_POS) & in qmspi_set_signalling_mode()
135 regs->MODE = (regs->MODE & ~(MCHP_QMSPI_M_SIG_MASK)) in qmspi_set_signalling_mode()
148 switch (config->operation & SPI_LINES_MASK) { in qmspi_config_get_lines()
179 const struct spi_qmspi_config *cfg = dev->config; in qmspi_configure()
180 struct spi_qmspi_data *data = dev->data; in qmspi_configure()
181 QMSPI_Type *regs = cfg->regs; in qmspi_configure()
184 if (spi_context_configured(&data->ctx, config)) { in qmspi_configure()
188 if (config->operation & SPI_HALF_DUPLEX) { in qmspi_configure()
189 return -ENOTSUP; in qmspi_configure()
192 if (config->operation & (SPI_TRANSFER_LSB | SPI_OP_MODE_SLAVE in qmspi_configure()
194 return -ENOTSUP; in qmspi_configure()
199 return -ENOTSUP; in qmspi_configure()
202 regs->CTRL = smode; in qmspi_configure()
205 qmspi_set_frequency(regs, config->frequency); in qmspi_configure()
208 if ((config->operation & SPI_MODE_CPHA) != 0U) { in qmspi_configure()
212 if ((config->operation & SPI_MODE_CPOL) != 0U) { in qmspi_configure()
218 if (SPI_WORD_SIZE_GET(config->operation) != 8) { in qmspi_configure()
219 return -ENOTSUP; in qmspi_configure()
223 smode = regs->MODE & ~(MCHP_QMSPI_M_CS_MASK); in qmspi_configure()
229 regs->MODE = smode; in qmspi_configure()
232 regs->CSTM = cfg->cs_timing; in qmspi_configure()
234 data->ctx.config = config; in qmspi_configure()
236 regs->MODE |= MCHP_QMSPI_M_ACTIVATE; in qmspi_configure()
242 * Transmit dummy clocks - QMSPI will generate requested number of
243 * SPI clocks with I/O pins tri-stated.
244 * Single mode: 1 bit per clock -> IFM field = 00b. Max 0x7fff clocks
245 * Dual mode: 2 bits per clock -> IFM field = 01b. Max 0x3fff clocks
246 * Quad mode: 4 bits per clock -> IFM field = 1xb. Max 0x1fff clocks
253 ifm = regs->CTRL & MCHP_QMSPI_C_IFM_MASK; in qmspi_tx_dummy_clocks()
266 regs->CTRL |= MCHP_QMSPI_C_DESCR_EN; in qmspi_tx_dummy_clocks()
267 regs->IEN = 0; in qmspi_tx_dummy_clocks()
268 regs->STS = 0xfffffffful; in qmspi_tx_dummy_clocks()
270 regs->EXE = MCHP_QMSPI_EXE_START; in qmspi_tx_dummy_clocks()
272 qstatus = regs->STS; in qmspi_tx_dummy_clocks()
274 return -EIO; in qmspi_tx_dummy_clocks()
282 * Return unit size power of 2 given number of bytes to transfer.
319 * QMSPI contains 16 32-bit descriptor registers used as a linked
320 * list of operations. Using only 32-bits there are limitations.
322 * be 1, 4, or 16 bytes. A descriptor can perform transmit or receive
334 return -EAGAIN; in qmspi_descr_alloc()
337 if (txb->len == 0) { in qmspi_descr_alloc()
342 descr = (regs->CTRL & MCHP_QMSPI_C_IFM_MASK); in qmspi_descr_alloc()
349 /* b[11:10] unit size 1, 4, or 16 bytes */ in qmspi_descr_alloc()
350 qshift = qlen_shift(txb->len); in qmspi_descr_alloc()
351 nu = txb->len >> qshift; in qmspi_descr_alloc()
373 return -EAGAIN; in qmspi_descr_alloc()
376 nu -= n; in qmspi_descr_alloc()
385 const uint8_t *p = tx_buf->buf; in qmspi_tx()
386 size_t tlen = tx_buf->len; in qmspi_tx()
394 /* Buffer pointer is NULL and number of bytes != 0 ? */ in qmspi_tx()
406 didx--; in qmspi_tx()
414 regs->CTRL = (regs->CTRL & MCHP_QMSPI_C_IFM_MASK) | in qmspi_tx()
416 regs->IEN = 0; in qmspi_tx()
417 regs->STS = 0xfffffffful; in qmspi_tx()
421 tlen--; in qmspi_tx()
425 if (regs->STS & MCHP_QMSPI_STS_TXBF_RO) { in qmspi_tx()
430 regs->EXE = MCHP_QMSPI_EXE_START; in qmspi_tx()
432 if (regs->STS & MCHP_QMSPI_STS_PROG_ERR) { in qmspi_tx()
433 return -EIO; in qmspi_tx()
438 while (regs->STS & MCHP_QMSPI_STS_TXBF_RO) { in qmspi_tx()
443 tlen--; in qmspi_tx()
448 if (regs->STS & MCHP_QMSPI_STS_DONE) { in qmspi_tx()
459 uint8_t *p = rx_buf->buf; in qmspi_rx()
460 size_t rlen = rx_buf->len; in qmspi_rx()
476 didx--; in qmspi_rx()
484 regs->CTRL = (regs->CTRL & MCHP_QMSPI_C_IFM_MASK) in qmspi_rx()
486 regs->IEN = 0; in qmspi_rx()
487 regs->STS = 0xfffffffful; in qmspi_rx()
492 * More clocks will be generated as we pull bytes from the RX FIFO. in qmspi_rx()
497 regs->EXE = MCHP_QMSPI_EXE_START; in qmspi_rx()
498 if (regs->STS & MCHP_QMSPI_STS_PROG_ERR) { in qmspi_rx()
499 return -EIO; in qmspi_rx()
503 if (!(regs->STS & MCHP_QMSPI_STS_RXBE_RO)) { in qmspi_rx()
508 rlen--; in qmspi_rx()
520 const struct spi_qmspi_config *cfg = dev->config; in qmspi_transceive()
521 struct spi_qmspi_data *data = dev->data; in qmspi_transceive()
522 QMSPI_Type *regs = cfg->regs; in qmspi_transceive()
529 spi_context_lock(&data->ctx, false, NULL, NULL, config); in qmspi_transceive()
536 spi_context_cs_control(&data->ctx, true); in qmspi_transceive()
539 ptx = tx_bufs->buffers; in qmspi_transceive()
540 nb = tx_bufs->count; in qmspi_transceive()
541 while (nb--) { in qmspi_transceive()
551 prx = rx_bufs->buffers; in qmspi_transceive()
552 nb = rx_bufs->count; in qmspi_transceive()
553 while (nb--) { in qmspi_transceive()
566 if (!(config->operation & SPI_HOLD_ON_CS)) { in qmspi_transceive()
568 last_didx = (regs->STS >> MCHP_QMSPI_C_NEXT_DESCR_POS) in qmspi_transceive()
572 regs->EXE = MCHP_QMSPI_EXE_STOP; in qmspi_transceive()
575 spi_context_cs_control(&data->ctx, false); in qmspi_transceive()
578 spi_context_release(&data->ctx, err); in qmspi_transceive()
597 return -ENOTSUP; in qmspi_transceive_async()
604 struct spi_qmspi_data *data = dev->data; in qmspi_release()
605 const struct spi_qmspi_config *cfg = dev->config; in qmspi_release()
606 QMSPI_Type *regs = cfg->regs; in qmspi_release()
608 /* Force CS# to de-assert on next unit boundary */ in qmspi_release()
609 regs->EXE = MCHP_QMSPI_EXE_STOP; in qmspi_release()
611 while (regs->STS & MCHP_QMSPI_STS_ACTIVE_RO) { in qmspi_release()
614 spi_context_unlock_unconditionally(&data->ctx); in qmspi_release()
629 const struct spi_qmspi_config *cfg = dev->config; in qmspi_init()
630 struct spi_qmspi_data *data = dev->data; in qmspi_init()
631 QMSPI_Type *regs = cfg->regs; in qmspi_init()
634 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); in qmspi_init()
642 regs->MODE = MCHP_QMSPI_M_SRST; in qmspi_init()
644 MCHP_GIRQ_CLR_EN(cfg->girq, cfg->girq_pos); in qmspi_init()
645 MCHP_GIRQ_SRC_CLR(cfg->girq, cfg->girq_pos); in qmspi_init()
647 MCHP_GIRQ_BLK_CLREN(cfg->girq); in qmspi_init()
648 NVIC_ClearPendingIRQ(cfg->girq_nvic_direct); in qmspi_init()
650 err = spi_context_cs_configure_all(&data->ctx); in qmspi_init()
655 spi_context_unlock_unconditionally(&data->ctx); in qmspi_init()