Lines Matching +full:high +full:- +full:side
4 * SPDX-License-Identifier: Apache-2.0
56 /* ------------ */
58 /* ------------ */
66 0x6101, /* 0: out pins, 1 side 0 [1] */
67 0x5101, /* 1: in pins, 1 side 1 [1] */
71 /* ------------ */
73 /* ------------ */
81 0x7021, /* 0: out x, 1 side 1 */
82 0xa101, /* 1: mov pins, x side 0 [1] */
83 0x5001, /* 2: in pins, 1 side 1 */
88 /* ------------------- */
90 /* ------------------- */
99 0x80a0, /* 0: pull block side 0 */
100 0x6001, /* 1: out pins, 1 side 0 */
101 0x10e1, /* 2: jmp !osre, 1 side 1 */
105 /* ------------------------- */
107 /* ------------------------- */
116 0x80a0, /* 0: pull block side 0 */
117 0x6020, /* 1: out x, 32 side 0 */
118 0x5001, /* 2: in pins, 1 side 1 */
119 0x0042, /* 3: jmp x--, 2 side 0 */
142 return spi_context_tx_on(&data->spi_ctx) || spi_context_rx_on(&data->spi_ctx); in spi_pico_pio_transfer_ongoing()
147 /* Do 8 bit accesses on FIFO, so that write data is byte-replicated. This */ in spi_pico_pio_sm_put8()
148 /* gets us the left-justification for free (for MSB-first shift-out) */ in spi_pico_pio_sm_put8()
149 io_rw_8 *txfifo = (io_rw_8 *)&pio->txf[sm]; in spi_pico_pio_sm_put8()
156 /* Do 8 bit accesses on FIFO, so that write data is byte-replicated. This */ in spi_pico_pio_sm_get8()
157 /* gets us the left-justification for free (for MSB-first shift-out) */ in spi_pico_pio_sm_get8()
158 io_rw_8 *rxfifo = (io_rw_8 *)&pio->rxf[sm]; in spi_pico_pio_sm_get8()
165 /* Do 16 bit accesses on FIFO, so that write data is halfword-replicated. This */ in spi_pico_pio_sm_put16()
166 /* gets us the left-justification for free (for MSB-first shift-out) */ in spi_pico_pio_sm_put16()
167 io_rw_16 *txfifo = (io_rw_16 *)&pio->txf[sm]; in spi_pico_pio_sm_put16()
174 io_rw_16 *rxfifo = (io_rw_16 *)&pio->rxf[sm]; in spi_pico_pio_sm_get16()
181 io_rw_32 *txfifo = (io_rw_32 *)&pio->txf[sm]; in spi_pico_pio_sm_put32()
188 io_rw_32 *rxfifo = (io_rw_32 *)&pio->rxf[sm]; in spi_pico_pio_sm_get32()
195 return ((data->pio->sm[data->pio_sm].addr == data->pio_tx_offset) && in spi_pico_pio_sm_complete()
196 pio_sm_is_tx_fifo_empty(data->pio, data->pio_sm)); in spi_pico_pio_sm_complete()
210 rc = clock_control_on(dev_cfg->clk_dev, dev_cfg->clk_id); in spi_pico_pio_configure()
216 rc = clock_control_get_rate(dev_cfg->clk_dev, dev_cfg->clk_id, &clock_freq); in spi_pico_pio_configure()
222 if (spi_context_configured(&data->spi_ctx, spi_cfg)) { in spi_pico_pio_configure()
226 if (spi_cfg->operation & SPI_OP_MODE_SLAVE) { in spi_pico_pio_configure()
228 return -ENOTSUP; in spi_pico_pio_configure()
232 /* "endianness" of the data. In MSB mode, the high-order bit of the */ in spi_pico_pio_configure()
233 /* most significant byte is sent first; in LSB mode, the low-order */ in spi_pico_pio_configure()
234 /* bit of the least-significant byte is sent first. */ in spi_pico_pio_configure()
235 if (spi_cfg->operation & SPI_TRANSFER_LSB) { in spi_pico_pio_configure()
240 if (spi_cfg->operation & (SPI_LINES_DUAL | SPI_LINES_QUAD | SPI_LINES_OCTAL)) { in spi_pico_pio_configure()
242 return -ENOTSUP; in spi_pico_pio_configure()
246 data->bits = SPI_WORD_SIZE_GET(spi_cfg->operation); in spi_pico_pio_configure()
248 if ((data->bits != 8) && (data->bits != 16) && (data->bits != 32)) { in spi_pico_pio_configure()
250 return -ENOTSUP; in spi_pico_pio_configure()
253 data->dfs = ((data->bits - 1) / 8) + 1; in spi_pico_pio_configure()
255 if (spi_cfg->operation & SPI_CS_ACTIVE_HIGH) { in spi_pico_pio_configure()
256 gpio_set_outover(data->spi_ctx.config->cs.gpio.pin, GPIO_OVERRIDE_INVERT); in spi_pico_pio_configure()
259 if (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPOL) { in spi_pico_pio_configure()
262 if (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPHA) { in spi_pico_pio_configure()
265 if (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_LOOP) { in spi_pico_pio_configure()
267 return -ENOTSUP; in spi_pico_pio_configure()
271 if (spi_cfg->operation & SPI_HALF_DUPLEX) { in spi_pico_pio_configure()
273 LOG_ERR("Only mode (0, 0) supported in 3-wire SIO"); in spi_pico_pio_configure()
274 return -ENOTSUP; in spi_pico_pio_configure()
277 if ((spi_cfg->frequency > spi_pico_pio_maximum_clock_frequency( in spi_pico_pio_configure()
279 (spi_cfg->frequency < spi_pico_pio_minimum_clock_frequency( in spi_pico_pio_configure()
281 LOG_ERR("clock-frequency out of range"); in spi_pico_pio_configure()
282 return -EINVAL; in spi_pico_pio_configure()
284 } else if (dev_cfg->sio_gpio.port) { in spi_pico_pio_configure()
285 LOG_ERR("SPI_HALF_DUPLEX operation needed for sio-gpios"); in spi_pico_pio_configure()
286 return -EINVAL; in spi_pico_pio_configure()
289 if (spi_cfg->operation & SPI_HALF_DUPLEX) { in spi_pico_pio_configure()
290 LOG_ERR("No sio-gpios defined, half-duplex not enabled"); in spi_pico_pio_configure()
291 return -EINVAL; in spi_pico_pio_configure()
295 clk = &dev_cfg->clk_gpio; in spi_pico_pio_configure()
296 data->pio = pio_rpi_pico_get_pio(dev_cfg->piodev); in spi_pico_pio_configure()
297 rc = pio_rpi_pico_allocate_sm(dev_cfg->piodev, &data->pio_sm); in spi_pico_pio_configure()
302 if (dev_cfg->sio_gpio.port) { in spi_pico_pio_configure()
304 const struct gpio_dt_spec *sio = &dev_cfg->sio_gpio; in spi_pico_pio_configure()
307 spi_cfg->frequency); in spi_pico_pio_configure()
309 data->pio_tx_offset = in spi_pico_pio_configure()
310 pio_add_program(data->pio, RPI_PICO_PIO_GET_PROGRAM(spi_sio_mode_0_0_tx)); in spi_pico_pio_configure()
312 data->pio_rx_offset = in spi_pico_pio_configure()
313 pio_add_program(data->pio, RPI_PICO_PIO_GET_PROGRAM(spi_sio_mode_0_0_rx)); in spi_pico_pio_configure()
314 data->pio_rx_wrap_target = in spi_pico_pio_configure()
315 data->pio_rx_offset + RPI_PICO_PIO_GET_WRAP_TARGET(spi_sio_mode_0_0_rx); in spi_pico_pio_configure()
316 data->pio_rx_wrap = in spi_pico_pio_configure()
317 data->pio_rx_offset + RPI_PICO_PIO_GET_WRAP(spi_sio_mode_0_0_rx); in spi_pico_pio_configure()
322 sm_config_set_in_pins(&sm_config, sio->pin); in spi_pico_pio_configure()
323 sm_config_set_in_shift(&sm_config, lsb, true, data->bits); in spi_pico_pio_configure()
324 sm_config_set_out_pins(&sm_config, sio->pin, 1); in spi_pico_pio_configure()
325 sm_config_set_out_shift(&sm_config, lsb, false, data->bits); in spi_pico_pio_configure()
326 hw_set_bits(&data->pio->input_sync_bypass, 1u << sio->pin); in spi_pico_pio_configure()
328 sm_config_set_sideset_pins(&sm_config, clk->pin); in spi_pico_pio_configure()
332 data->pio_tx_offset + RPI_PICO_PIO_GET_WRAP_TARGET(spi_sio_mode_0_0_tx), in spi_pico_pio_configure()
333 data->pio_tx_offset + RPI_PICO_PIO_GET_WRAP(spi_sio_mode_0_0_tx)); in spi_pico_pio_configure()
335 pio_sm_set_pindirs_with_mask(data->pio, data->pio_sm, in spi_pico_pio_configure()
336 (BIT(clk->pin) | BIT(sio->pin)), in spi_pico_pio_configure()
337 (BIT(clk->pin) | BIT(sio->pin))); in spi_pico_pio_configure()
338 pio_sm_set_pins_with_mask(data->pio, data->pio_sm, 0, in spi_pico_pio_configure()
339 BIT(clk->pin) | BIT(sio->pin)); in spi_pico_pio_configure()
340 pio_gpio_init(data->pio, sio->pin); in spi_pico_pio_configure()
341 pio_gpio_init(data->pio, clk->pin); in spi_pico_pio_configure()
343 pio_sm_init(data->pio, data->pio_sm, data->pio_tx_offset, &sm_config); in spi_pico_pio_configure()
344 pio_sm_set_enabled(data->pio, data->pio_sm, true); in spi_pico_pio_configure()
346 LOG_ERR("SIO pin requires half-duplex support"); in spi_pico_pio_configure()
347 return -EINVAL; in spi_pico_pio_configure()
350 /* 4-wire mode */ in spi_pico_pio_configure()
351 const struct gpio_dt_spec *miso = miso = &dev_cfg->miso_gpio; in spi_pico_pio_configure()
352 const struct gpio_dt_spec *mosi = &dev_cfg->mosi_gpio; in spi_pico_pio_configure()
370 return -ENOTSUP; in spi_pico_pio_configure()
373 if ((spi_cfg->frequency > in spi_pico_pio_configure()
375 (spi_cfg->frequency < in spi_pico_pio_configure()
377 LOG_ERR("clock-frequency out of range"); in spi_pico_pio_configure()
378 return -EINVAL; in spi_pico_pio_configure()
382 spi_pico_pio_clock_divisor(clock_freq, cycles, spi_cfg->frequency); in spi_pico_pio_configure()
384 if (!pio_can_add_program(data->pio, program)) { in spi_pico_pio_configure()
385 return -EBUSY; in spi_pico_pio_configure()
388 data->pio_tx_offset = pio_add_program(data->pio, program); in spi_pico_pio_configure()
392 sm_config_set_in_pins(&sm_config, miso->pin); in spi_pico_pio_configure()
393 sm_config_set_in_shift(&sm_config, lsb, true, data->bits); in spi_pico_pio_configure()
394 sm_config_set_out_pins(&sm_config, mosi->pin, 1); in spi_pico_pio_configure()
395 sm_config_set_out_shift(&sm_config, lsb, true, data->bits); in spi_pico_pio_configure()
396 sm_config_set_sideset_pins(&sm_config, clk->pin); in spi_pico_pio_configure()
398 sm_config_set_wrap(&sm_config, data->pio_tx_offset + wrap_target, in spi_pico_pio_configure()
399 data->pio_tx_offset + wrap); in spi_pico_pio_configure()
401 pio_sm_set_consecutive_pindirs(data->pio, data->pio_sm, miso->pin, 1, false); in spi_pico_pio_configure()
402 pio_sm_set_pindirs_with_mask(data->pio, data->pio_sm, in spi_pico_pio_configure()
403 (BIT(clk->pin) | BIT(mosi->pin)), in spi_pico_pio_configure()
404 (BIT(clk->pin) | BIT(mosi->pin))); in spi_pico_pio_configure()
405 pio_sm_set_pins_with_mask(data->pio, data->pio_sm, (cpol << clk->pin), in spi_pico_pio_configure()
406 BIT(clk->pin) | BIT(mosi->pin)); in spi_pico_pio_configure()
407 pio_gpio_init(data->pio, mosi->pin); in spi_pico_pio_configure()
408 pio_gpio_init(data->pio, miso->pin); in spi_pico_pio_configure()
409 pio_gpio_init(data->pio, clk->pin); in spi_pico_pio_configure()
411 pio_sm_init(data->pio, data->pio_sm, data->pio_tx_offset, &sm_config); in spi_pico_pio_configure()
412 pio_sm_set_enabled(data->pio, data->pio_sm, true); in spi_pico_pio_configure()
415 data->spi_ctx.config = spi_cfg; in spi_pico_pio_configure()
422 struct spi_pico_pio_data *data = dev->data; in spi_pico_pio_txrx_4_wire()
423 const size_t chunk_len = spi_context_max_continuous_chunk(&data->spi_ctx); in spi_pico_pio_txrx_4_wire()
424 const uint8_t *txbuf = data->spi_ctx.tx_buf; in spi_pico_pio_txrx_4_wire()
425 uint8_t *rxbuf = data->spi_ctx.rx_buf; in spi_pico_pio_txrx_4_wire()
429 data->tx_count = 0; in spi_pico_pio_txrx_4_wire()
430 data->rx_count = 0; in spi_pico_pio_txrx_4_wire()
432 pio_sm_clear_fifos(data->pio, data->pio_sm); in spi_pico_pio_txrx_4_wire()
434 while (data->rx_count < chunk_len || data->tx_count < chunk_len) { in spi_pico_pio_txrx_4_wire()
436 while ((!pio_sm_is_tx_fifo_full(data->pio, data->pio_sm)) && in spi_pico_pio_txrx_4_wire()
437 data->tx_count < chunk_len && fifo_cnt < PIO_FIFO_DEPTH) { in spi_pico_pio_txrx_4_wire()
441 switch (data->dfs) { in spi_pico_pio_txrx_4_wire()
444 txrx = sys_get_be32(txbuf + (data->tx_count * 4)); in spi_pico_pio_txrx_4_wire()
446 spi_pico_pio_sm_put32(data->pio, data->pio_sm, txrx); in spi_pico_pio_txrx_4_wire()
451 txrx = sys_get_be16(txbuf + (data->tx_count * 2)); in spi_pico_pio_txrx_4_wire()
453 spi_pico_pio_sm_put16(data->pio, data->pio_sm, txrx); in spi_pico_pio_txrx_4_wire()
458 txrx = ((uint8_t *)txbuf)[data->tx_count]; in spi_pico_pio_txrx_4_wire()
460 spi_pico_pio_sm_put8(data->pio, data->pio_sm, txrx); in spi_pico_pio_txrx_4_wire()
464 LOG_ERR("Support fot %d bits not enabled", (data->dfs * 8)); in spi_pico_pio_txrx_4_wire()
467 data->tx_count++; in spi_pico_pio_txrx_4_wire()
471 while ((!pio_sm_is_rx_fifo_empty(data->pio, data->pio_sm)) && in spi_pico_pio_txrx_4_wire()
472 data->rx_count < chunk_len && fifo_cnt > 0) { in spi_pico_pio_txrx_4_wire()
473 switch (data->dfs) { in spi_pico_pio_txrx_4_wire()
475 txrx = spi_pico_pio_sm_get32(data->pio, data->pio_sm); in spi_pico_pio_txrx_4_wire()
479 sys_put_be32(txrx, rxbuf + (data->rx_count * 4)); in spi_pico_pio_txrx_4_wire()
484 txrx = spi_pico_pio_sm_get16(data->pio, data->pio_sm); in spi_pico_pio_txrx_4_wire()
488 sys_put_be16(txrx, rxbuf + (data->rx_count * 2)); in spi_pico_pio_txrx_4_wire()
493 txrx = spi_pico_pio_sm_get8(data->pio, data->pio_sm); in spi_pico_pio_txrx_4_wire()
497 ((uint8_t *)rxbuf)[data->rx_count] = (uint8_t)txrx; in spi_pico_pio_txrx_4_wire()
502 LOG_ERR("Support fot %d bits not enabled", (data->dfs * 8)); in spi_pico_pio_txrx_4_wire()
505 data->rx_count++; in spi_pico_pio_txrx_4_wire()
506 fifo_cnt--; in spi_pico_pio_txrx_4_wire()
514 struct spi_pico_pio_data *data = dev->data; in spi_pico_pio_txrx_3_wire()
515 const struct spi_pico_pio_config *dev_cfg = dev->config; in spi_pico_pio_txrx_3_wire()
516 const uint8_t *txbuf = data->spi_ctx.tx_buf; in spi_pico_pio_txrx_3_wire()
517 uint8_t *rxbuf = data->spi_ctx.rx_buf; in spi_pico_pio_txrx_3_wire()
519 int sio_pin = dev_cfg->sio_gpio.pin; in spi_pico_pio_txrx_3_wire()
520 uint32_t tx_size = data->spi_ctx.tx_len; /* Number of WORDS to send */ in spi_pico_pio_txrx_3_wire()
521 uint32_t rx_size = data->spi_ctx.rx_len; /* Number of WORDS to receive */ in spi_pico_pio_txrx_3_wire()
523 data->tx_count = 0; in spi_pico_pio_txrx_3_wire()
524 data->rx_count = 0; in spi_pico_pio_txrx_3_wire()
527 pio_sm_set_enabled(data->pio, data->pio_sm, false); in spi_pico_pio_txrx_3_wire()
528 pio_sm_set_wrap(data->pio, data->pio_sm, in spi_pico_pio_txrx_3_wire()
529 data->pio_tx_offset + in spi_pico_pio_txrx_3_wire()
531 data->pio_tx_offset + RPI_PICO_PIO_GET_WRAP(spi_sio_mode_0_0_tx)); in spi_pico_pio_txrx_3_wire()
532 pio_sm_clear_fifos(data->pio, data->pio_sm); in spi_pico_pio_txrx_3_wire()
533 pio_sm_set_pindirs_with_mask(data->pio, data->pio_sm, BIT(sio_pin), BIT(sio_pin)); in spi_pico_pio_txrx_3_wire()
534 pio_sm_restart(data->pio, data->pio_sm); in spi_pico_pio_txrx_3_wire()
535 pio_sm_clkdiv_restart(data->pio, data->pio_sm); in spi_pico_pio_txrx_3_wire()
536 pio_sm_exec(data->pio, data->pio_sm, pio_encode_jmp(data->pio_tx_offset)); in spi_pico_pio_txrx_3_wire()
537 pio_sm_set_enabled(data->pio, data->pio_sm, true); in spi_pico_pio_txrx_3_wire()
539 while (data->tx_count < tx_size) { in spi_pico_pio_txrx_3_wire()
541 while ((!pio_sm_is_tx_fifo_full(data->pio, data->pio_sm)) && in spi_pico_pio_txrx_3_wire()
542 data->tx_count < tx_size) { in spi_pico_pio_txrx_3_wire()
544 switch (data->dfs) { in spi_pico_pio_txrx_3_wire()
546 txrx = sys_get_be32(txbuf + (data->tx_count * 4)); in spi_pico_pio_txrx_3_wire()
547 spi_pico_pio_sm_put32(data->pio, data->pio_sm, txrx); in spi_pico_pio_txrx_3_wire()
551 txrx = sys_get_be16(txbuf + (data->tx_count * 2)); in spi_pico_pio_txrx_3_wire()
552 spi_pico_pio_sm_put16(data->pio, data->pio_sm, txrx); in spi_pico_pio_txrx_3_wire()
556 txrx = ((uint8_t *)txbuf)[data->tx_count]; in spi_pico_pio_txrx_3_wire()
557 spi_pico_pio_sm_put8(data->pio, data->pio_sm, txrx); in spi_pico_pio_txrx_3_wire()
561 LOG_ERR("Support fot %d bits not enabled", (data->dfs * 8)); in spi_pico_pio_txrx_3_wire()
564 data->tx_count++; in spi_pico_pio_txrx_3_wire()
569 while ((!pio_sm_is_tx_fifo_empty(data->pio, data->pio_sm)) || in spi_pico_pio_txrx_3_wire()
575 pio_sm_set_enabled(data->pio, data->pio_sm, false); in spi_pico_pio_txrx_3_wire()
576 pio_sm_set_wrap(data->pio, data->pio_sm, data->pio_rx_wrap_target, in spi_pico_pio_txrx_3_wire()
577 data->pio_rx_wrap); in spi_pico_pio_txrx_3_wire()
578 pio_sm_clear_fifos(data->pio, data->pio_sm); in spi_pico_pio_txrx_3_wire()
579 pio_sm_set_pindirs_with_mask(data->pio, data->pio_sm, 0, BIT(sio_pin)); in spi_pico_pio_txrx_3_wire()
580 pio_sm_restart(data->pio, data->pio_sm); in spi_pico_pio_txrx_3_wire()
581 pio_sm_clkdiv_restart(data->pio, data->pio_sm); in spi_pico_pio_txrx_3_wire()
582 pio_sm_put(data->pio, data->pio_sm, (rx_size * data->bits) - 1); in spi_pico_pio_txrx_3_wire()
583 pio_sm_exec(data->pio, data->pio_sm, pio_encode_jmp(data->pio_rx_offset)); in spi_pico_pio_txrx_3_wire()
584 pio_sm_set_enabled(data->pio, data->pio_sm, true); in spi_pico_pio_txrx_3_wire()
586 while (data->rx_count < rx_size) { in spi_pico_pio_txrx_3_wire()
587 while ((!pio_sm_is_rx_fifo_empty(data->pio, data->pio_sm)) && in spi_pico_pio_txrx_3_wire()
588 data->rx_count < rx_size) { in spi_pico_pio_txrx_3_wire()
590 switch (data->dfs) { in spi_pico_pio_txrx_3_wire()
592 txrx = spi_pico_pio_sm_get32(data->pio, data->pio_sm); in spi_pico_pio_txrx_3_wire()
593 sys_put_be32(txrx, rxbuf + (data->rx_count * 4)); in spi_pico_pio_txrx_3_wire()
597 txrx = spi_pico_pio_sm_get16(data->pio, data->pio_sm); in spi_pico_pio_txrx_3_wire()
598 sys_put_be16(txrx, rxbuf + (data->rx_count * 2)); in spi_pico_pio_txrx_3_wire()
602 txrx = spi_pico_pio_sm_get8(data->pio, data->pio_sm); in spi_pico_pio_txrx_3_wire()
603 rxbuf[data->rx_count] = (uint8_t)txrx; in spi_pico_pio_txrx_3_wire()
607 LOG_ERR("Support fot %d bits not enabled", (data->dfs * 8)); in spi_pico_pio_txrx_3_wire()
610 data->rx_count++; in spi_pico_pio_txrx_3_wire()
615 LOG_ERR("SIO pin requires half-duplex support"); in spi_pico_pio_txrx_3_wire()
621 const struct spi_pico_pio_config *dev_cfg = dev->config; in spi_pico_pio_txrx()
623 /* 3-wire or 4-wire mode? */ in spi_pico_pio_txrx()
624 if (dev_cfg->sio_gpio.port) { in spi_pico_pio_txrx()
636 const struct spi_pico_pio_config *dev_cfg = dev->config; in spi_pico_pio_transceive_impl()
637 struct spi_pico_pio_data *data = dev->data; in spi_pico_pio_transceive_impl()
638 struct spi_context *spi_ctx = &data->spi_ctx; in spi_pico_pio_transceive_impl()
648 spi_context_buffers_setup(spi_ctx, tx_bufs, rx_bufs, data->dfs); in spi_pico_pio_transceive_impl()
653 spi_context_update_tx(spi_ctx, 1, data->tx_count); in spi_pico_pio_transceive_impl()
654 spi_context_update_rx(spi_ctx, 1, data->rx_count); in spi_pico_pio_transceive_impl()
674 struct spi_pico_pio_data *data = dev->data; in spi_pico_pio_release()
676 spi_context_unlock_unconditionally(&data->spi_ctx); in spi_pico_pio_release()
690 if (!device_is_ready(gpio->port)) { in config_gpio()
692 return -ENODEV; in config_gpio()
706 const struct spi_pico_pio_config *dev_cfg = dev->config; in spi_pico_pio_init()
707 struct spi_pico_pio_data *data = dev->data; in spi_pico_pio_init()
710 rc = pinctrl_apply_state(dev_cfg->pin_cfg, PINCTRL_STATE_DEFAULT); in spi_pico_pio_init()
716 rc = config_gpio(&dev_cfg->clk_gpio, "clk", GPIO_OUTPUT_ACTIVE); in spi_pico_pio_init()
721 if (dev_cfg->mosi_gpio.port != NULL) { in spi_pico_pio_init()
722 rc = config_gpio(&dev_cfg->mosi_gpio, "mosi", GPIO_OUTPUT); in spi_pico_pio_init()
728 if (dev_cfg->miso_gpio.port != NULL) { in spi_pico_pio_init()
729 rc = config_gpio(&dev_cfg->miso_gpio, "miso", GPIO_INPUT); in spi_pico_pio_init()
735 rc = spi_context_cs_configure_all(&data->spi_ctx); in spi_pico_pio_init()
741 spi_context_unlock_unconditionally(&data->spi_ctx); in spi_pico_pio_init()