Lines Matching +full:tx +full:- +full:dtc

3  * SPDX-License-Identifier: Apache-2.0
48 /* TX */
59 struct device *dev = (struct device *)p_args->p_context; in spi_cb()
60 struct ra_spi_data *data = dev->data; in spi_cb()
62 switch (p_args->event) { in spi_cb()
64 spi_context_cs_control(&data->ctx, false); in spi_cb()
65 spi_context_complete(&data->ctx, dev, 0); in spi_cb()
73 spi_context_cs_control(&data->ctx, false); in spi_cb()
74 spi_context_complete(&data->ctx, dev, -EIO); in spi_cb()
83 struct ra_spi_data *data = dev->data; in ra_spi_configure()
86 if (spi_context_configured(&data->ctx, config)) { in ra_spi_configure()
91 if (data->spi.open != 0) { in ra_spi_configure()
92 R_SPI_Close(&data->spi); in ra_spi_configure()
95 if ((config->operation & SPI_FRAME_FORMAT_TI) == SPI_FRAME_FORMAT_TI) { in ra_spi_configure()
96 return -ENOTSUP; in ra_spi_configure()
99 if (config->operation & SPI_OP_MODE_SLAVE) { in ra_spi_configure()
100 data->fsp_config.operating_mode = SPI_MODE_SLAVE; in ra_spi_configure()
102 data->fsp_config.operating_mode = SPI_MODE_MASTER; in ra_spi_configure()
105 if (SPI_MODE_GET(config->operation) & SPI_MODE_CPOL) { in ra_spi_configure()
106 data->fsp_config.clk_polarity = SPI_CLK_POLARITY_HIGH; in ra_spi_configure()
108 data->fsp_config.clk_polarity = SPI_CLK_POLARITY_LOW; in ra_spi_configure()
111 if (SPI_MODE_GET(config->operation) & SPI_MODE_CPHA) { in ra_spi_configure()
112 data->fsp_config.clk_phase = SPI_CLK_PHASE_EDGE_EVEN; in ra_spi_configure()
114 if (data->fsp_config.operating_mode == SPI_MODE_MASTER) { in ra_spi_configure()
115 data->fsp_config.clk_phase = SPI_CLK_PHASE_EDGE_ODD; in ra_spi_configure()
118 return -EINVAL; in ra_spi_configure()
122 if (config->operation & SPI_TRANSFER_LSB) { in ra_spi_configure()
123 data->fsp_config.bit_order = SPI_BIT_ORDER_LSB_FIRST; in ra_spi_configure()
125 data->fsp_config.bit_order = SPI_BIT_ORDER_MSB_FIRST; in ra_spi_configure()
128 if (config->operation & SPI_CS_ACTIVE_HIGH) { in ra_spi_configure()
129 data->fsp_config_extend.ssl_polarity = SPI_SSLP_HIGH; in ra_spi_configure()
131 data->fsp_config_extend.ssl_polarity = SPI_SSLP_LOW; in ra_spi_configure()
134 if (!(config->operation & SPI_OP_MODE_SLAVE)) { in ra_spi_configure()
135 LOG_INF("frequency: %d", config->frequency); in ra_spi_configure()
136 fsp_err = R_SPI_CalculateBitrate(config->frequency, in ra_spi_configure()
137 &data->fsp_config_extend.spck_div); in ra_spi_configure()
140 return -EIO; in ra_spi_configure()
144 data->fsp_config_extend.spi_comm = SPI_COMMUNICATION_FULL_DUPLEX; in ra_spi_configure()
146 data->fsp_config_extend.spi_clksyn = SPI_SSL_MODE_CLK_SYN; in ra_spi_configure()
148 data->fsp_config_extend.spi_clksyn = SPI_SSL_MODE_SPI; in ra_spi_configure()
149 data->fsp_config_extend.ssl_select = SPI_SSL_SELECT_SSL0; in ra_spi_configure()
152 data->fsp_config.p_extend = &data->fsp_config_extend; in ra_spi_configure()
154 data->fsp_config.p_callback = spi_cb; in ra_spi_configure()
155 data->fsp_config.p_context = dev; in ra_spi_configure()
156 fsp_err = R_SPI_Open(&data->spi, &data->fsp_config); in ra_spi_configure()
159 return -EIO; in ra_spi_configure()
161 data->ctx.config = config; in ra_spi_configure()
169 return (spi_context_tx_on(&data->ctx) || spi_context_rx_on(&data->ctx)); in ra_spi_transfer_ongoing()
171 if (spi_context_total_tx_len(&data->ctx) < spi_context_total_rx_len(&data->ctx)) { in ra_spi_transfer_ongoing()
172 return (spi_context_tx_on(&data->ctx) || spi_context_rx_on(&data->ctx)); in ra_spi_transfer_ongoing()
174 return (spi_context_tx_on(&data->ctx) && spi_context_rx_on(&data->ctx)); in ra_spi_transfer_ongoing()
182 R_SPI0_Type *p_spi_reg = data->spi.p_regs; in ra_spi_transceive_slave()
184 (spi_bit_width_t)(SPI_WORD_SIZE_GET(data->ctx.config->operation) - 1); in ra_spi_transceive_slave()
186 if (p_spi_reg->SPSR_b.SPTEF && spi_context_tx_buf_on(&data->ctx)) { in ra_spi_transceive_slave()
187 uint32_t tx; in ra_spi_transceive_slave() local
189 if (data->ctx.tx_buf != NULL) { in ra_spi_transceive_slave()
190 if (data->dfs > 2) { in ra_spi_transceive_slave()
191 tx = *(uint32_t *)(data->ctx.tx_buf); in ra_spi_transceive_slave()
192 } else if (data->dfs > 1) { in ra_spi_transceive_slave()
193 tx = *(uint16_t *)(data->ctx.tx_buf); in ra_spi_transceive_slave()
195 tx = *(uint8_t *)(data->ctx.tx_buf); in ra_spi_transceive_slave()
198 tx = 0; in ra_spi_transceive_slave()
203 p_spi_reg->SPDR = (uint32_t)tx; in ra_spi_transceive_slave()
205 p_spi_reg->SPDR_BY = (uint8_t)tx; in ra_spi_transceive_slave()
207 p_spi_reg->SPDR_HA = (uint16_t)tx; in ra_spi_transceive_slave()
210 spi_context_update_tx(&data->ctx, data->dfs, 1); in ra_spi_transceive_slave()
212 p_spi_reg->SPCR_b.SPTIE = 0; in ra_spi_transceive_slave()
215 if (p_spi_reg->SPSR_b.SPRF && spi_context_rx_buf_on(&data->ctx)) { in ra_spi_transceive_slave()
220 rx = (uint32_t)p_spi_reg->SPDR; in ra_spi_transceive_slave()
222 rx = (uint8_t)p_spi_reg->SPDR_BY; in ra_spi_transceive_slave()
224 rx = (uint16_t)p_spi_reg->SPDR_HA; in ra_spi_transceive_slave()
227 if (data->dfs > 2) { in ra_spi_transceive_slave()
228 UNALIGNED_PUT(rx, (uint32_t *)data->ctx.rx_buf); in ra_spi_transceive_slave()
229 } else if (data->dfs > 1) { in ra_spi_transceive_slave()
230 UNALIGNED_PUT(rx, (uint16_t *)data->ctx.rx_buf); in ra_spi_transceive_slave()
232 UNALIGNED_PUT(rx, (uint8_t *)data->ctx.rx_buf); in ra_spi_transceive_slave()
234 spi_context_update_rx(&data->ctx, data->dfs, 1); in ra_spi_transceive_slave()
242 R_SPI0_Type *p_spi_reg = data->spi.p_regs; in ra_spi_transceive_master()
244 (spi_bit_width_t)(SPI_WORD_SIZE_GET(data->ctx.config->operation) - 1); in ra_spi_transceive_master()
245 uint32_t tx; in ra_spi_transceive_master() local
248 /* Tx transfer */ in ra_spi_transceive_master()
249 if (spi_context_tx_buf_on(&data->ctx)) { in ra_spi_transceive_master()
250 if (data->dfs > 2) { in ra_spi_transceive_master()
251 tx = *(uint32_t *)(data->ctx.tx_buf); in ra_spi_transceive_master()
252 } else if (data->dfs > 1) { in ra_spi_transceive_master()
253 tx = *(uint16_t *)(data->ctx.tx_buf); in ra_spi_transceive_master()
255 tx = *(uint8_t *)(data->ctx.tx_buf); in ra_spi_transceive_master()
258 tx = 0U; in ra_spi_transceive_master()
261 while (!p_spi_reg->SPSR_b.SPTEF) { in ra_spi_transceive_master()
266 p_spi_reg->SPDR = (uint32_t)tx; in ra_spi_transceive_master()
268 p_spi_reg->SPDR_BY = (uint8_t)tx; in ra_spi_transceive_master()
270 p_spi_reg->SPDR_HA = (uint16_t)tx; in ra_spi_transceive_master()
273 spi_context_update_tx(&data->ctx, data->dfs, 1); in ra_spi_transceive_master()
275 if (p_spi_reg->SPCR_b.TXMD == 0x0) { in ra_spi_transceive_master()
276 while (!p_spi_reg->SPSR_b.SPRF) { in ra_spi_transceive_master()
281 rx = (uint32_t)p_spi_reg->SPDR; in ra_spi_transceive_master()
283 rx = (uint8_t)p_spi_reg->SPDR_BY; in ra_spi_transceive_master()
285 rx = (uint16_t)p_spi_reg->SPDR_HA; in ra_spi_transceive_master()
288 if (spi_context_rx_buf_on(&data->ctx)) { in ra_spi_transceive_master()
289 if (data->dfs > 2) { in ra_spi_transceive_master()
290 UNALIGNED_PUT(rx, (uint32_t *)data->ctx.rx_buf); in ra_spi_transceive_master()
291 } else if (data->dfs > 1) { in ra_spi_transceive_master()
292 UNALIGNED_PUT(rx, (uint16_t *)data->ctx.rx_buf); in ra_spi_transceive_master()
294 UNALIGNED_PUT(rx, (uint8_t *)data->ctx.rx_buf); in ra_spi_transceive_master()
297 spi_context_update_rx(&data->ctx, data->dfs, 1); in ra_spi_transceive_master()
306 uint16_t operation = data->ctx.config->operation; in ra_spi_transceive_data()
322 struct ra_spi_data *data = dev->data; in transceive()
332 return -ENOTSUP; in transceive()
336 spi_context_lock(&data->ctx, asynchronous, cb, userdata, config); in transceive()
342 data->dfs = ((SPI_WORD_SIZE_GET(config->operation) - 1) / 8) + 1; in transceive()
343 p_spi_reg = data->spi.p_regs; in transceive()
345 (spi_bit_width_t)(SPI_WORD_SIZE_GET(data->ctx.config->operation) - 1); in transceive()
347 spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, data->dfs); in transceive()
349 spi_context_cs_control(&data->ctx, true); in transceive()
352 if (data->ctx.rx_len == 0) { in transceive()
353 data->data_len = spi_context_is_slave(&data->ctx) in transceive()
354 ? spi_context_total_tx_len(&data->ctx) in transceive()
355 : data->ctx.tx_len; in transceive()
356 } else if (data->ctx.tx_len == 0) { in transceive()
357 data->data_len = spi_context_is_slave(&data->ctx) in transceive()
358 ? spi_context_total_rx_len(&data->ctx) in transceive()
359 : data->ctx.rx_len; in transceive()
361 data->data_len = spi_context_is_slave(&data->ctx) in transceive()
362 ? MAX(spi_context_total_tx_len(&data->ctx), in transceive()
363 spi_context_total_rx_len(&data->ctx)) in transceive()
364 : MIN(data->ctx.tx_len, data->ctx.rx_len); in transceive()
367 if (data->ctx.rx_buf == NULL) { in transceive()
368 R_SPI_Write(&data->spi, data->ctx.tx_buf, data->data_len, spi_width); in transceive()
369 } else if (data->ctx.tx_buf == NULL) { in transceive()
370 R_SPI_Read(&data->spi, data->ctx.rx_buf, data->data_len, spi_width); in transceive()
372 R_SPI_WriteRead(&data->spi, data->ctx.tx_buf, data->ctx.rx_buf, data->data_len, in transceive()
376 ret = spi_context_wait_for_completion(&data->ctx); in transceive()
379 p_spi_reg->SPCR_b.TXMD = (0x0); in transceive()
380 if (!spi_context_tx_on(&data->ctx)) { in transceive()
381 p_spi_reg->SPCR_b.TXMD = 0x0; in transceive()
383 if (!spi_context_rx_on(&data->ctx)) { in transceive()
384 p_spi_reg->SPCR_b.TXMD = 0x1; /* tx only */ in transceive()
387 uint32_t spdcr = p_spi_reg->SPDCR; in transceive()
394 /* Set SPBYT so 8bit transfer works with the DTC/DMAC. */ in transceive()
397 /* Configure Half-Word access to data register. */ in transceive()
405 bit_width = ((bit_width + 1) >> 2) - 5; in transceive()
407 p_spi_reg->SPDCR = (uint8_t)spdcr; in transceive()
408 p_spi_reg->SPCMD[0] |= bit_width << 8; in transceive()
411 p_spi_reg->SPCR |= R_SPI0_SPCR_SPE_Msk; in transceive()
418 while (p_spi_reg->SPSR_b.IDLNF) { in transceive()
421 p_spi_reg->SPCR_b.SPE = 0; in transceive()
423 spi_context_cs_control(&data->ctx, false); in transceive()
424 spi_context_complete(&data->ctx, dev, 0); in transceive()
427 if (spi_context_is_slave(&data->ctx) && !ret) { in transceive()
428 ret = data->ctx.recv_frames; in transceive()
433 spi_context_release(&data->ctx, ret); in transceive()
456 struct ra_spi_data *data = dev->data; in ra_spi_release()
458 spi_context_unlock_unconditionally(&data->ctx); in ra_spi_release()
471 const struct ra_spi_config *config = dev->config; in spi_ra_init()
472 struct ra_spi_data *data = dev->data; in spi_ra_init()
476 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); in spi_ra_init()
481 ret = spi_context_cs_configure_all(&data->ctx); in spi_ra_init()
486 spi_context_unlock_unconditionally(&data->ctx); in spi_ra_init()
496 (spi_bit_width_t)(SPI_WORD_SIZE_GET(data->ctx.config->operation) - 1); in ra_spi_retransmit()
498 if (data->ctx.rx_len == 0) { in ra_spi_retransmit()
499 data->data_len = data->ctx.tx_len; in ra_spi_retransmit()
500 data->spi.p_tx_data = data->ctx.tx_buf; in ra_spi_retransmit()
501 data->spi.p_rx_data = NULL; in ra_spi_retransmit()
502 } else if (data->ctx.tx_len == 0) { in ra_spi_retransmit()
503 data->data_len = data->ctx.rx_len; in ra_spi_retransmit()
504 data->spi.p_tx_data = NULL; in ra_spi_retransmit()
505 data->spi.p_rx_data = data->ctx.rx_buf; in ra_spi_retransmit()
507 data->data_len = MIN(data->ctx.tx_len, data->ctx.rx_len); in ra_spi_retransmit()
508 data->spi.p_tx_data = data->ctx.tx_buf; in ra_spi_retransmit()
509 data->spi.p_rx_data = data->ctx.rx_buf; in ra_spi_retransmit()
512 data->spi.bit_width = spi_width; in ra_spi_retransmit()
513 data->spi.rx_count = 0; in ra_spi_retransmit()
514 data->spi.tx_count = 0; in ra_spi_retransmit()
515 data->spi.count = data->data_len; in ra_spi_retransmit()
518 /* Determine DTC transfer size */ in ra_spi_retransmit()
529 if (data->spi.p_cfg->p_transfer_rx) { in ra_spi_retransmit()
531 data->spi.rx_count = data->data_len; in ra_spi_retransmit()
534 (transfer_instance_t *)data->spi.p_cfg->p_transfer_rx; in ra_spi_retransmit()
535 transfer_info_t *p_info = p_transfer_rx->p_cfg->p_info; in ra_spi_retransmit()
538 p_info->transfer_settings_word_b.size = size; in ra_spi_retransmit()
539 p_info->length = (uint16_t)data->data_len; in ra_spi_retransmit()
540 p_info->transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED; in ra_spi_retransmit()
541 p_info->p_dest = data->ctx.rx_buf; in ra_spi_retransmit()
543 if (NULL == data->ctx.rx_buf) { in ra_spi_retransmit()
546 p_info->transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_FIXED; in ra_spi_retransmit()
547 p_info->p_dest = &dummy_rx; in ra_spi_retransmit()
550 p_transfer_rx->p_api->reconfigure(p_transfer_rx->p_ctrl, p_info); in ra_spi_retransmit()
553 if (data->spi.p_cfg->p_transfer_tx) { in ra_spi_retransmit()
555 data->spi.tx_count = data->data_len; in ra_spi_retransmit()
558 (transfer_instance_t *)data->spi.p_cfg->p_transfer_tx; in ra_spi_retransmit()
559 transfer_info_t *p_info = p_transfer_tx->p_cfg->p_info; in ra_spi_retransmit()
562 p_info->transfer_settings_word_b.size = size; in ra_spi_retransmit()
563 p_info->length = (uint16_t)data->data_len; in ra_spi_retransmit()
564 p_info->transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED; in ra_spi_retransmit()
565 p_info->p_src = data->ctx.tx_buf; in ra_spi_retransmit()
567 if (NULL == data->ctx.tx_buf) { in ra_spi_retransmit()
570 p_info->transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_FIXED; in ra_spi_retransmit()
571 p_info->p_src = &dummy_tx; in ra_spi_retransmit()
573 R_SPI0_Type *p_spi_reg = data->spi.p_regs; in ra_spi_retransmit()
575 p_transfer_tx->p_api->reconfigure(p_transfer_tx->p_ctrl, p_info); in ra_spi_retransmit()
578 p_spi_reg->SPCR |= R_SPI0_SPCR_SPE_Msk; in ra_spi_retransmit()
590 struct ra_spi_data *data = dev->data; in ra_spi_rxi_isr()
594 if (spi_context_is_slave(&data->ctx) && data->spi.rx_count == data->spi.count) { in ra_spi_rxi_isr()
595 if (data->ctx.rx_buf != NULL && data->ctx.tx_buf != NULL) { in ra_spi_rxi_isr()
596 data->ctx.recv_frames = MIN(spi_context_total_tx_len(&data->ctx), in ra_spi_rxi_isr()
597 spi_context_total_rx_len(&data->ctx)); in ra_spi_rxi_isr()
598 } else if (data->ctx.tx_buf == NULL) { in ra_spi_rxi_isr()
599 data->ctx.recv_frames = data->data_len; in ra_spi_rxi_isr()
601 R_BSP_IrqDisable(data->fsp_config.tei_irq); in ra_spi_rxi_isr()
606 R_BSP_IrqDisable(data->fsp_config.txi_irq); in ra_spi_rxi_isr()
609 data->spi.p_regs->SPCR_b.SPE = 0; in ra_spi_rxi_isr()
611 /* Re-enable the TXI IRQ and clear the pending IRQ. */ in ra_spi_rxi_isr()
612 R_BSP_IrqEnable(data->fsp_config.txi_irq); in ra_spi_rxi_isr()
614 spi_context_cs_control(&data->ctx, false); in ra_spi_rxi_isr()
615 spi_context_complete(&data->ctx, dev, 0); in ra_spi_rxi_isr()
629 struct ra_spi_data *data = dev->data; in ra_spi_tei_isr()
630 R_SPI0_Type *p_spi_reg = data->spi.p_regs; in ra_spi_tei_isr()
632 if (data->spi.rx_count == data->spi.count) { in ra_spi_tei_isr()
633 spi_context_update_rx(&data->ctx, 1, data->data_len); in ra_spi_tei_isr()
635 if (data->spi.tx_count == data->spi.count) { in ra_spi_tei_isr()
636 spi_context_update_tx(&data->ctx, 1, data->data_len); in ra_spi_tei_isr()
640 R_BSP_IrqDisable(data->spi.p_cfg->txi_irq); in ra_spi_tei_isr()
642 p_spi_reg->SPCR_b.SPE = 0U; in ra_spi_tei_isr()
644 p_spi_reg->SPSR; in ra_spi_tei_isr()
645 p_spi_reg->SPSR = 0; in ra_spi_tei_isr()
646 R_BSP_IrqEnable(data->spi.p_cfg->txi_irq); in ra_spi_tei_isr()
650 p_spi_reg->SPCR |= R_SPI0_SPCR_SPE_Msk; in ra_spi_tei_isr()
653 R_ICU->IELSR_b[data->fsp_config.tei_irq].IR = 0U; in ra_spi_tei_isr()
683 R_ICU->IELSR[DT_INST_IRQ_BY_NAME(index, rxi, irq)] = \
685 R_ICU->IELSR[DT_INST_IRQ_BY_NAME(index, txi, irq)] = \
687 R_ICU->IELSR[DT_INST_IRQ_BY_NAME(index, tei, irq)] = \
689 R_ICU->IELSR[DT_INST_IRQ_BY_NAME(index, eri, irq)] = \