Lines Matching refs:spi_pw_reg_write
30 static void spi_pw_reg_write(const struct device *dev, in spi_pw_reg_write() function
40 spi_pw_reg_write(dev, PW_SPI_REG_RESETS, 0x00); in spi_pw_ssp_reset()
41 spi_pw_reg_write(dev, PW_SPI_REG_RESETS, PW_SPI_INST_RESET); in spi_pw_ssp_reset()
57 spi_pw_reg_write(dev, PW_SPI_REG_CS_CTRL, cs_ctrl); in spi_pw_enable_cs_hw_ctrl()
75 spi_pw_reg_write(dev, PW_SPI_REG_CS_CTRL, cs_ctrl); in spi_pw_cs_sw_ctrl()
90 spi_pw_reg_write(dev, PW_SPI_REG_CTRLR1, ctrlr1); in spi_pw_intr_enable()
99 spi_pw_reg_write(dev, PW_SPI_REG_CTRLR1, ctrlr1); in spi_pw_intr_disable()
109 spi_pw_reg_write(dev, PW_SPI_REG_CTRLR0, ctrlr0); in spi_pw_ssp_enable()
119 spi_pw_reg_write(dev, PW_SPI_REG_CTRLR0, ctrlr0); in spi_pw_ssp_disable()
180 spi_pw_reg_write(dev, PW_SPI_REG_CS_CTRL, cs_ctrl); in spi_pw_cs_ctrl_init()
202 spi_pw_reg_write(dev, PW_SPI_REG_SITF, reg_data); in spi_pw_tx_thld_set()
217 spi_pw_reg_write(dev, PW_SPI_REG_SIRF, reg_data); in spi_pw_rx_thld_set()
247 spi_pw_reg_write(dev, PW_SPI_REG_CTRLR0, ctrlr0); in spi_pw_set_data_size()
287 spi_pw_reg_write(dev, PW_SPI_REG_CTRLR1, ctrlr1); in spi_pw_config_phase_polarity()
300 spi_pw_reg_write(dev, PW_SPI_REG_CLKS, clks); in spi_pw_enable_clk()
321 spi_pw_reg_write(dev, PW_SPI_REG_CTRLR0, ctrlr0); in spi_pw_config_clk()
361 spi_pw_reg_write(dev, PW_SPI_REG_SSSR, sssr); in spi_pw_clear_intr()
393 spi_pw_reg_write(dev, PW_SPI_REG_SITF, tx_fifo_level); in spi_pw_reset_tx_fifo_level()
405 spi_pw_reg_write(dev, PW_SPI_REG_SIRF, rx_fifo_level); in spi_pw_update_rx_fifo_level()
453 spi_pw_reg_write(dev, PW_SPI_REG_SSDR, data); in spi_pw_tx_data()