105 	uint32_t ctrlr0;  in spi_pw_ssp_enable()  local
107 	ctrlr0 = spi_pw_reg_read(dev, PW_SPI_REG_CTRLR0);  in spi_pw_ssp_enable()
108 	ctrlr0 |= PW_SPI_CTRLR0_SSE_BIT;  in spi_pw_ssp_enable()
109 	spi_pw_reg_write(dev, PW_SPI_REG_CTRLR0, ctrlr0);  in spi_pw_ssp_enable()
115 	uint32_t ctrlr0;  in spi_pw_ssp_disable()  local
117 	ctrlr0 = spi_pw_reg_read(dev, PW_SPI_REG_CTRLR0);  in spi_pw_ssp_disable()
118 	ctrlr0 &= ~(PW_SPI_CTRLR0_SSE_BIT);  in spi_pw_ssp_disable()
119 	spi_pw_reg_write(dev, PW_SPI_REG_CTRLR0, ctrlr0);  in spi_pw_ssp_disable()
223 	uint32_t ctrlr0;  in spi_pw_set_data_size()  local
225 	ctrlr0 = spi_pw_reg_read(dev, PW_SPI_REG_CTRLR0);  in spi_pw_set_data_size()
228 	ctrlr0 &= ~(PW_SPI_CTRLR0_MOD_BIT);  in spi_pw_set_data_size()
230 	ctrlr0 &= PW_SPI_CTRLR0_DATA_MASK;  in spi_pw_set_data_size()
231 	ctrlr0 &= PW_SPI_CTRLR0_EDSS_MASK;  in spi_pw_set_data_size()
235 		ctrlr0 |= PW_SPI_DATA_SIZE_4_BIT;  in spi_pw_set_data_size()
237 		ctrlr0 |= PW_SPI_DATA_SIZE_8_BIT;  in spi_pw_set_data_size()
239 		ctrlr0 |= PW_SPI_DATA_SIZE_16_BIT;  in spi_pw_set_data_size()
241 		ctrlr0 |= PW_SPI_DATA_SIZE_32_BIT;  in spi_pw_set_data_size()
247 	spi_pw_reg_write(dev, PW_SPI_REG_CTRLR0, ctrlr0);  in spi_pw_set_data_size()
307 	uint32_t ctrlr0, scr;  in spi_pw_config_clk()  local
317 	ctrlr0 = spi_pw_reg_read(dev, PW_SPI_REG_CTRLR0);  in spi_pw_config_clk()
319 	ctrlr0 &= ~(PW_SPI_SCR_MASK);  in spi_pw_config_clk()
320 	ctrlr0 |= (scr << PW_SPI_SCR_SHIFT);  in spi_pw_config_clk()
321 	spi_pw_reg_write(dev, PW_SPI_REG_CTRLR0, ctrlr0);  in spi_pw_config_clk()