3  * SPDX-License-Identifier: Apache-2.0
47 	return spi_context_tx_on(&spi->ctx) || spi_context_rx_on(&spi->ctx);  in is_spi_transfer_ongoing()
132 	uint8_t dfs = SPI_WORD_SIZE_GET(config->operation);  in spi_pw_get_frame_size()
137 		LOG_WRN("Unsupported dfs, 1-byte size will be used");  in spi_pw_get_frame_size()
146 	struct spi_pw_data *spi = dev->data;  in spi_pw_cs_ctrl_enable()
149 		if (spi->cs_mode == CS_SW_MODE) {  in spi_pw_cs_ctrl_enable()
151 		} else if (spi->cs_mode == CS_GPIO_MODE) {  in spi_pw_cs_ctrl_enable()
152 			spi_context_cs_control(&spi->ctx, true);  in spi_pw_cs_ctrl_enable()
155 		if (spi->cs_mode == CS_SW_MODE) {  in spi_pw_cs_ctrl_enable()
157 		} else if (spi->cs_mode == CS_GPIO_MODE) {  in spi_pw_cs_ctrl_enable()
158 			spi_context_cs_control(&spi->ctx, false);  in spi_pw_cs_ctrl_enable()
166 	struct spi_pw_data *spi = dev->data;  in spi_pw_cs_ctrl_init()
171 	if (spi->cs_output == PW_SPI_CS1_OUTPUT_SELECT) {  in spi_pw_cs_ctrl_init()
182 	if (spi->cs_mode == CS_HW_MODE) {  in spi_pw_cs_ctrl_init()
184 	} else if (spi->cs_mode == CS_SW_MODE) {  in spi_pw_cs_ctrl_init()
186 	} else if (spi->cs_mode == CS_GPIO_MODE) {  in spi_pw_cs_ctrl_init()
214 	if (spi->ctx.rx_len && spi->ctx.rx_len < spi->fifo_depth) {  in spi_pw_rx_thld_set()
215 		reg_data = spi->ctx.rx_len - 1;  in spi_pw_rx_thld_set()
234 	if (SPI_WORD_SIZE_GET(config->operation) == 4) {  in spi_pw_set_data_size()
236 	} else if (SPI_WORD_SIZE_GET(config->operation) == 8) {  in spi_pw_set_data_size()
238 	} else if (SPI_WORD_SIZE_GET(config->operation) == 16) {  in spi_pw_set_data_size()
240 	} else if (SPI_WORD_SIZE_GET(config->operation) == 32) {  in spi_pw_set_data_size()
244 		return -ENOTSUP;  in spi_pw_set_data_size()
260 	mode = (SPI_MODE_GET(config->operation) & SPI_MODE_CPOL) |  in spi_pw_config_phase_polarity()
261 	       (SPI_MODE_GET(config->operation) & SPI_MODE_CPHA);  in spi_pw_config_phase_polarity()
286 	/* Set Polarity & Phase  */  in spi_pw_config_phase_polarity()
310 	if (!config->frequency) {  in spi_pw_config_clk()
312 	} else if (config->frequency > PW_SPI_BR_MAX_FRQ) {  in spi_pw_config_clk()
313 		scr = (info->clock_freq / PW_SPI_BR_MAX_FRQ) - 1;  in spi_pw_config_clk()
315 		scr = (info->clock_freq / config->frequency) - 1;  in spi_pw_config_clk()
326 	struct spi_pw_data *spi = dev->data;  in spi_pw_completed()
328 	if (!err && (spi_context_tx_on(&spi->ctx) ||  in spi_pw_completed()
329 		     spi_context_rx_on(&spi->ctx))) {  in spi_pw_completed()
352 	spi_context_complete(&spi->ctx, dev, err);  in spi_pw_completed()
410 	struct spi_pw_data *spi = dev->data;  in spi_pw_tx_data()
414 	if (spi_context_rx_on(&spi->ctx)) {  in spi_pw_tx_data()
415 		fifo_len = spi->fifo_depth -  in spi_pw_tx_data()
416 			   spi_pw_get_tx_fifo_level(dev) -  in spi_pw_tx_data()
422 		fifo_len = spi->fifo_depth - spi_pw_get_tx_fifo_level(dev);  in spi_pw_tx_data()
426 		if (spi_context_tx_buf_on(&spi->ctx)) {  in spi_pw_tx_data()
427 			switch (spi->dfs) {  in spi_pw_tx_data()
430 						     (spi->ctx.tx_buf));  in spi_pw_tx_data()
434 						     (spi->ctx.tx_buf));  in spi_pw_tx_data()
438 						     (spi->ctx.tx_buf));  in spi_pw_tx_data()
441 		} else if (spi_context_rx_on(&spi->ctx)) {  in spi_pw_tx_data()
442 			if ((int)(spi->ctx.rx_len - spi->fifo_diff) <= 0) {  in spi_pw_tx_data()
447 		} else if (spi_context_tx_on(&spi->ctx)) {  in spi_pw_tx_data()
455 		spi_context_update_tx(&spi->ctx, spi->dfs, 1);  in spi_pw_tx_data()
456 		spi->fifo_diff++;  in spi_pw_tx_data()
457 		fifo_len--;  in spi_pw_tx_data()
460 	if (!spi_context_tx_on(&spi->ctx)) {  in spi_pw_tx_data()
467 	struct spi_pw_data *spi = dev->data;  in spi_pw_rx_data()
472 		if (spi_context_rx_buf_on(&spi->ctx)) {  in spi_pw_rx_data()
473 			switch (spi->dfs) {  in spi_pw_rx_data()
476 					      (uint8_t *)spi->ctx.rx_buf);  in spi_pw_rx_data()
480 					      (uint16_t *)spi->ctx.rx_buf);  in spi_pw_rx_data()
484 					      (uint32_t *)spi->ctx.rx_buf);  in spi_pw_rx_data()
489 		spi_context_update_rx(&spi->ctx, spi->dfs, 1);  in spi_pw_rx_data()
490 		spi->fifo_diff--;  in spi_pw_rx_data()
493 	if (!spi->ctx.rx_len && spi->ctx.tx_len < spi->fifo_depth) {  in spi_pw_rx_data()
494 		spi_pw_update_rx_fifo_level(spi->ctx.tx_len - 1, dev);  in spi_pw_rx_data()
495 	} else if (spi_pw_get_rx_fifo_level(dev) >= spi->ctx.rx_len) {  in spi_pw_rx_data()
496 		spi_pw_update_rx_fifo_level(spi->ctx.rx_len - 1, dev);  in spi_pw_rx_data()
509 		err = -EIO;  in spi_pw_transfer()
515 		err = -EIO;  in spi_pw_transfer()
521 		err = -EIO;  in spi_pw_transfer()
551 	spi->ctx.config = config;  in spi_pw_configure()
553 	if (!spi_cs_is_gpio(spi->ctx.config)) {  in spi_pw_configure()
554 		if (spi->cs_mode == CS_GPIO_MODE) {  in spi_pw_configure()
556 			spi->cs_mode = CS_HW_MODE;  in spi_pw_configure()
561 	if (config->operation & SPI_HALF_DUPLEX) {  in spi_pw_configure()
562 		LOG_ERR("Half-duplex not supported");  in spi_pw_configure()
563 		return -ENOTSUP;  in spi_pw_configure()
567 	if (config->operation & SPI_OP_MODE_SLAVE) {  in spi_pw_configure()
569 		return -ENOTSUP;  in spi_pw_configure()
572 	if ((config->operation & SPI_TRANSFER_LSB) ||  in spi_pw_configure()
574 	     (config->operation & (SPI_LINES_DUAL |  in spi_pw_configure()
578 		return -EINVAL;  in spi_pw_configure()
581 	if (config->operation & SPI_FRAME_FORMAT_TI) {  in spi_pw_configure()
583 		return -ENOTSUP;  in spi_pw_configure()
586 	if (config->operation & SPI_HOLD_ON_CS) {  in spi_pw_configure()
588 		return -ENOTSUP;  in spi_pw_configure()
596 		return -ENOTSUP;  in spi_pw_configure()
599 	/* Set Polarity & Phase  */  in spi_pw_configure()
619 	const struct spi_pw_config *info = dev->config;  in transceive()
620 	struct spi_pw_data *spi = dev->data;  in transceive()
630 		return -ENOTSUP;  in transceive()
633 	spi_context_lock(&spi->ctx, asynchronous, cb, userdata, config);  in transceive()
643 	spi->dfs = spi_pw_get_frame_size(config);  in transceive()
644 	spi_context_buffers_setup(&spi->ctx, tx_bufs, rx_bufs,  in transceive()
645 				  spi->dfs);  in transceive()
647 	spi->fifo_diff = 0U;  in transceive()
670 	err = spi_context_wait_for_completion(&spi->ctx);  in transceive()
682 	spi_context_release(&spi->ctx, err);  in transceive()
715 	struct spi_pw_data *spi = dev->data;  in spi_pw_release()
717 	if (!spi_context_configured(&spi->ctx, config)) {  in spi_pw_release()
718 		return -EINVAL;  in spi_pw_release()
721 	spi_context_unlock_unconditionally(&spi->ctx);  in spi_pw_release()
750 	const struct spi_pw_config *info = dev->config;  in spi_pw_init()
751 	struct spi_pw_data *spi = dev->data;  in spi_pw_init()
755 	if (info->pcie) {  in spi_pw_init()
758 		if (info->pcie->bdf == PCIE_BDF_NONE) {  in spi_pw_init()
760 			return -ENODEV;  in spi_pw_init()
763 		if (!pcie_probe_mbar(info->pcie->bdf, 0, &mbar)) {  in spi_pw_init()
765 			return -EINVAL;  in spi_pw_init()
768 		pcie_set_cmd(info->pcie->bdf, PCIE_CONF_CMDSTAT_MEM,  in spi_pw_init()
774 		pcie_set_cmd(info->pcie->bdf,  in spi_pw_init()
799 	info->irq_config(dev);  in spi_pw_init()
802 	if (spi->cs_mode == CS_GPIO_MODE) {  in spi_pw_init()
803 		err = spi_context_cs_configure_all(&spi->ctx);  in spi_pw_init()
810 	spi_context_unlock_unconditionally(&spi->ctx);  in spi_pw_init()
837 		const struct spi_pw_config *info = dev->config;		     \
840 			irq = pcie_alloc_irq(info->pcie->bdf);		     \
846 			pcie_conf_write(info->pcie->bdf,		     \
849 		pcie_connect_dynamic_irq(info->pcie->bdf, irq,		     \
854 		pcie_irq_enable(info->pcie->bdf, irq);			     \