Lines Matching +full:max +full:- +full:xfer +full:- +full:size
6 * SPDX-License-Identifier: Apache-2.0
48 struct spi_psoc6_transfer xfer; member
53 const struct spi_psoc6_config *config = dev->config; in spi_psoc6_transfer_next_packet()
54 struct spi_psoc6_data *data = dev->data; in spi_psoc6_transfer_next_packet()
55 struct spi_context *ctx = &data->ctx; in spi_psoc6_transfer_next_packet()
56 struct spi_psoc6_transfer *xfer = &data->xfer; in spi_psoc6_transfer_next_packet() local
59 LOG_DBG("TX L: %d, RX L: %d", ctx->tx_len, ctx->rx_len); in spi_psoc6_transfer_next_packet()
61 if ((ctx->tx_len == 0U) && (ctx->rx_len == 0U)) { in spi_psoc6_transfer_next_packet()
63 xfer->dataSize = 0U; in spi_psoc6_transfer_next_packet()
70 if (ctx->tx_len == 0U) { in spi_psoc6_transfer_next_packet()
72 xfer->txData = NULL; in spi_psoc6_transfer_next_packet()
73 xfer->rxData = ctx->rx_buf; in spi_psoc6_transfer_next_packet()
74 xfer->dataSize = ctx->rx_len; in spi_psoc6_transfer_next_packet()
75 } else if (ctx->rx_len == 0U) { in spi_psoc6_transfer_next_packet()
77 xfer->txData = (uint8_t *) ctx->tx_buf; in spi_psoc6_transfer_next_packet()
78 xfer->rxData = NULL; in spi_psoc6_transfer_next_packet()
79 xfer->dataSize = ctx->tx_len; in spi_psoc6_transfer_next_packet()
80 } else if (ctx->tx_len == ctx->rx_len) { in spi_psoc6_transfer_next_packet()
82 xfer->txData = (uint8_t *) ctx->tx_buf; in spi_psoc6_transfer_next_packet()
83 xfer->rxData = ctx->rx_buf; in spi_psoc6_transfer_next_packet()
84 xfer->dataSize = ctx->tx_len; in spi_psoc6_transfer_next_packet()
85 } else if (ctx->tx_len > ctx->rx_len) { in spi_psoc6_transfer_next_packet()
90 xfer->txData = (uint8_t *) ctx->tx_buf; in spi_psoc6_transfer_next_packet()
91 xfer->rxData = ctx->rx_buf; in spi_psoc6_transfer_next_packet()
92 xfer->dataSize = ctx->rx_len; in spi_psoc6_transfer_next_packet()
98 xfer->txData = (uint8_t *) ctx->tx_buf; in spi_psoc6_transfer_next_packet()
99 xfer->rxData = ctx->rx_buf; in spi_psoc6_transfer_next_packet()
100 xfer->dataSize = ctx->tx_len; in spi_psoc6_transfer_next_packet()
103 if (xfer->txData != NULL) { in spi_psoc6_transfer_next_packet()
104 if (Cy_SCB_SPI_WriteArray(config->base, xfer->txData, in spi_psoc6_transfer_next_packet()
105 xfer->dataSize) != xfer->dataSize) { in spi_psoc6_transfer_next_packet()
113 for (count = 0U; count < xfer->dataSize; count++) { in spi_psoc6_transfer_next_packet()
114 if (Cy_SCB_SPI_Write(config->base, 0U) == 0U) { in spi_psoc6_transfer_next_packet()
120 LOG_DBG("TRX L: %d", xfer->dataSize); in spi_psoc6_transfer_next_packet()
125 xfer->dataSize = 0U; in spi_psoc6_transfer_next_packet()
128 spi_context_complete(ctx, dev, -ENOMEM); in spi_psoc6_transfer_next_packet()
133 const struct spi_psoc6_config *config = dev->config; in spi_psoc6_isr()
134 struct spi_psoc6_data *data = dev->data; in spi_psoc6_isr()
136 Cy_SCB_ClearMasterInterrupt(config->base, in spi_psoc6_isr()
140 if (data->xfer.rxData != NULL) { in spi_psoc6_isr()
141 Cy_SCB_SPI_ReadArray(config->base, in spi_psoc6_isr()
142 data->xfer.rxData, in spi_psoc6_isr()
143 data->xfer.dataSize); in spi_psoc6_isr()
145 Cy_SCB_ClearRxFifo(config->base); in spi_psoc6_isr()
149 spi_context_update_tx(&data->ctx, 1, data->xfer.dataSize); in spi_psoc6_isr()
150 spi_context_update_rx(&data->ctx, 1, data->xfer.dataSize); in spi_psoc6_isr()
157 Cy_SCB_SetMasterInterruptMask(config->base, 0U); in spi_psoc6_isr()
161 if (data->xfer.dataSize > 0U) { in spi_psoc6_isr()
162 Cy_SCB_SetMasterInterruptMask(config->base, in spi_psoc6_isr()
173 * Currently the bus freq is fixed to 50Mhz and max SPI clk can be in spi_psoc6_get_freqdiv()
189 cfg->spiMode = CY_SCB_SPI_MASTER; in spi_psoc6_master_get_defaults()
190 cfg->subMode = CY_SCB_SPI_MOTOROLA; in spi_psoc6_master_get_defaults()
191 cfg->sclkMode = 0U; in spi_psoc6_master_get_defaults()
192 cfg->oversample = 0U; in spi_psoc6_master_get_defaults()
193 cfg->rxDataWidth = 0U; in spi_psoc6_master_get_defaults()
194 cfg->txDataWidth = 0U; in spi_psoc6_master_get_defaults()
195 cfg->enableMsbFirst = false; in spi_psoc6_master_get_defaults()
196 cfg->enableFreeRunSclk = false; in spi_psoc6_master_get_defaults()
197 cfg->enableInputFilter = false; in spi_psoc6_master_get_defaults()
198 cfg->enableMisoLateSample = false; in spi_psoc6_master_get_defaults()
199 cfg->enableTransferSeperation = false; in spi_psoc6_master_get_defaults()
200 cfg->ssPolarity = 0U; in spi_psoc6_master_get_defaults()
201 cfg->enableWakeFromSleep = false; in spi_psoc6_master_get_defaults()
202 cfg->rxFifoTriggerLevel = 0U; in spi_psoc6_master_get_defaults()
203 cfg->rxFifoIntEnableMask = 0U; in spi_psoc6_master_get_defaults()
204 cfg->txFifoTriggerLevel = 0U; in spi_psoc6_master_get_defaults()
205 cfg->txFifoIntEnableMask = 0U; in spi_psoc6_master_get_defaults()
206 cfg->masterSlaveIntEnableMask = 0U; in spi_psoc6_master_get_defaults()
212 struct spi_psoc6_data *data = dev->data; in spi_psoc6_configure()
215 if (spi_context_configured(&data->ctx, spi_cfg)) { in spi_psoc6_configure()
220 if (spi_cfg->operation & SPI_HALF_DUPLEX) { in spi_psoc6_configure()
221 LOG_ERR("Half-duplex not supported"); in spi_psoc6_configure()
222 return -ENOTSUP; in spi_psoc6_configure()
225 word_size = SPI_WORD_SIZE_GET(spi_cfg->operation); in spi_psoc6_configure()
227 LOG_ERR("Word size %d is greater than %d", in spi_psoc6_configure()
229 return -EINVAL; in spi_psoc6_configure()
232 if (SPI_OP_MODE_GET(spi_cfg->operation) == SPI_OP_MODE_MASTER) { in spi_psoc6_configure()
233 spi_psoc6_master_get_defaults(&data->cfg); in spi_psoc6_configure()
235 if (spi_cfg->slave > SPI_CHIP_SELECT_COUNT) { in spi_psoc6_configure()
237 spi_cfg->slave, SPI_CHIP_SELECT_COUNT); in spi_psoc6_configure()
238 return -EINVAL; in spi_psoc6_configure()
241 data->cfg.rxDataWidth = data->cfg.txDataWidth = word_size; in spi_psoc6_configure()
243 if (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPHA) { in spi_psoc6_configure()
244 if (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPOL) { in spi_psoc6_configure()
245 data->cfg.sclkMode = CY_SCB_SPI_CPHA1_CPOL1; in spi_psoc6_configure()
247 data->cfg.sclkMode = CY_SCB_SPI_CPHA1_CPOL0; in spi_psoc6_configure()
250 if (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPOL) { in spi_psoc6_configure()
251 data->cfg.sclkMode = CY_SCB_SPI_CPHA0_CPOL1; in spi_psoc6_configure()
253 data->cfg.sclkMode = CY_SCB_SPI_CPHA0_CPOL0; in spi_psoc6_configure()
257 data->cfg.enableMsbFirst = !!!(spi_cfg->operation & in spi_psoc6_configure()
259 data->cfg.oversample = spi_psoc6_get_freqdiv(spi_cfg->frequency); in spi_psoc6_configure()
261 data->ctx.config = spi_cfg; in spi_psoc6_configure()
264 return -ENOTSUP; in spi_psoc6_configure()
272 const struct spi_psoc6_config *config = dev->config; in spi_psoc6_transceive_sync_loop()
273 struct spi_psoc6_data *data = dev->data; in spi_psoc6_transceive_sync_loop()
275 while (data->xfer.dataSize > 0U) { in spi_psoc6_transceive_sync_loop()
276 while (!Cy_SCB_IsTxComplete(config->base)) { in spi_psoc6_transceive_sync_loop()
280 if (data->xfer.rxData != NULL) { in spi_psoc6_transceive_sync_loop()
281 Cy_SCB_SPI_ReadArray(config->base, in spi_psoc6_transceive_sync_loop()
282 data->xfer.rxData, in spi_psoc6_transceive_sync_loop()
283 data->xfer.dataSize); in spi_psoc6_transceive_sync_loop()
285 Cy_SCB_ClearRxFifo(config->base); in spi_psoc6_transceive_sync_loop()
288 spi_context_update_tx(&data->ctx, 1, data->xfer.dataSize); in spi_psoc6_transceive_sync_loop()
289 spi_context_update_rx(&data->ctx, 1, data->xfer.dataSize); in spi_psoc6_transceive_sync_loop()
303 const struct spi_psoc6_config *config = dev->config; in spi_psoc6_transceive()
304 struct spi_psoc6_data *data = dev->data; in spi_psoc6_transceive()
307 spi_context_lock(&data->ctx, asynchronous, cb, userdata, spi_cfg); in spi_psoc6_transceive()
316 Cy_SCB_SPI_Init(config->base, &data->cfg, NULL); in spi_psoc6_transceive()
317 Cy_SCB_SPI_SetActiveSlaveSelect(config->base, spi_cfg->slave); in spi_psoc6_transceive()
318 Cy_SCB_SPI_Enable(config->base); in spi_psoc6_transceive()
320 spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1); in spi_psoc6_transceive()
322 spi_context_cs_control(&data->ctx, true); in spi_psoc6_transceive()
327 Cy_SCB_SetMasterInterruptMask(config->base, in spi_psoc6_transceive()
333 ret = spi_context_wait_for_completion(&data->ctx); in spi_psoc6_transceive()
335 Cy_SCB_SPI_Disable(config->base, NULL); in spi_psoc6_transceive()
338 spi_context_release(&data->ctx, ret); in spi_psoc6_transceive()
368 struct spi_psoc6_data *data = dev->data; in spi_psoc6_release()
370 spi_context_unlock_unconditionally(&data->ctx); in spi_psoc6_release()
378 const struct spi_psoc6_config *config = dev->config; in spi_psoc6_init()
379 struct spi_psoc6_data *data = dev->data; in spi_psoc6_init()
383 err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); in spi_psoc6_init()
388 Cy_SysClk_PeriphAssignDivider(config->periph_id, in spi_psoc6_init()
397 config->irq_config_func(dev); in spi_psoc6_init()
400 err = spi_context_cs_configure_all(&data->ctx); in spi_psoc6_init()