Lines Matching +full:out +full:- +full:active +full:- +full:low
2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
15 struct spi_context *ctx = &data->ctx; in spi_nxp_s32_last_packet()
17 if (ctx->tx_count <= 1U && ctx->rx_count <= 1U) { in spi_nxp_s32_last_packet()
18 if (!spi_context_tx_on(ctx) && (data->transfer_len == ctx->rx_len)) { in spi_nxp_s32_last_packet()
22 if (!spi_context_rx_on(ctx) && (data->transfer_len == ctx->tx_len)) { in spi_nxp_s32_last_packet()
26 if ((ctx->rx_len == ctx->tx_len) && (data->transfer_len == ctx->tx_len)) { in spi_nxp_s32_last_packet()
41 const struct spi_nxp_s32_config *config = dev->config; in spi_nxp_s32_transfer_next_packet()
42 struct spi_nxp_s32_data *data = dev->data; in spi_nxp_s32_transfer_next_packet()
49 data_cb = config->cb; in spi_nxp_s32_transfer_next_packet()
54 data->transfer_len = spi_context_max_continuous_chunk(&data->ctx); in spi_nxp_s32_transfer_next_packet()
55 data->transfer_len = MIN(data->transfer_len, in spi_nxp_s32_transfer_next_packet()
56 SPI_NXP_S32_MAX_BYTES_PER_PACKAGE(data->bytes_per_frame)); in spi_nxp_s32_transfer_next_packet()
60 Spi_Ip_UpdateTransferParam(&data->transfer_cfg, ¶m); in spi_nxp_s32_transfer_next_packet()
62 status = Spi_Ip_AsyncTransmit(&data->transfer_cfg, (uint8_t *)data->ctx.tx_buf, in spi_nxp_s32_transfer_next_packet()
63 data->ctx.rx_buf, data->transfer_len, data_cb); in spi_nxp_s32_transfer_next_packet()
67 return -EIO; in spi_nxp_s32_transfer_next_packet()
74 while (Spi_Ip_GetStatus(config->spi_hw_cfg->Instance) == SPI_IP_BUSY) { in spi_nxp_s32_transfer_next_packet()
75 Spi_Ip_ManageBuffers(config->spi_hw_cfg->Instance); in spi_nxp_s32_transfer_next_packet()
78 if (Spi_Ip_GetStatus(config->spi_hw_cfg->Instance) == SPI_IP_FAULT) { in spi_nxp_s32_transfer_next_packet()
79 return -EIO; in spi_nxp_s32_transfer_next_packet()
99 uint32_t low, high; in spi_nxp_s32_getbestfreq() local
112 low = 0U; in spi_nxp_s32_getbestfreq()
113 high = SPI_NXP_S32_NUM_SCALER - 1U; in spi_nxp_s32_getbestfreq()
117 scaler = (low + high) / 2U; in spi_nxp_s32_getbestfreq()
127 low = scaler; in spi_nxp_s32_getbestfreq()
133 if ((requested_baud - best_freq) > (requested_baud - curr_freq)) { in spi_nxp_s32_getbestfreq()
135 best_baud->prescaler = prescaler; in spi_nxp_s32_getbestfreq()
136 best_baud->scaler = scaler; in spi_nxp_s32_getbestfreq()
143 } while ((high - low) > 1U); in spi_nxp_s32_getbestfreq()
145 if ((high - low) <= 1U) { in spi_nxp_s32_getbestfreq()
148 /* use low value */ in spi_nxp_s32_getbestfreq()
149 scaler = low; in spi_nxp_s32_getbestfreq()
159 if ((requested_baud - best_freq) > (requested_baud - curr_freq)) { in spi_nxp_s32_getbestfreq()
161 best_baud->prescaler = prescaler; in spi_nxp_s32_getbestfreq()
162 best_baud->scaler = scaler; in spi_nxp_s32_getbestfreq()
172 best_baud->frequency = best_freq; in spi_nxp_s32_getbestfreq()
186 uint32_t low, high; in spi_nxp_s32_getbestdelay() local
196 low = 0U; in spi_nxp_s32_getbestdelay()
197 high = SPI_NXP_S32_NUM_SCALER - 1U; in spi_nxp_s32_getbestdelay()
200 scaler = (low + high) / 2U; in spi_nxp_s32_getbestdelay()
210 low = scaler; in spi_nxp_s32_getbestdelay()
216 if ((best_delay - requested_delay) > (current_delay - requested_delay)) { in spi_nxp_s32_getbestdelay()
226 } while ((high - low) > 1U); in spi_nxp_s32_getbestdelay()
228 if ((high - low) <= 1U) { in spi_nxp_s32_getbestdelay()
231 /* use low value */ in spi_nxp_s32_getbestdelay()
232 scaler = low; in spi_nxp_s32_getbestdelay()
241 if ((best_delay - requested_delay) > in spi_nxp_s32_getbestdelay()
242 (current_delay - requested_delay)) { in spi_nxp_s32_getbestdelay()
258 *best_prescaler = SPI_NXP_S32_NUM_PRESCALER - 1U; in spi_nxp_s32_getbestdelay()
259 *best_scaler = SPI_NXP_S32_NUM_SCALER - 1U; in spi_nxp_s32_getbestdelay()
266 const struct spi_nxp_s32_config *config = dev->config; in spi_nxp_s32_configure()
267 struct spi_nxp_s32_data *data = dev->data; in spi_nxp_s32_configure()
279 if (spi_context_configured(&data->ctx, spi_cfg)) { in spi_nxp_s32_configure()
284 err = clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_rate); in spi_nxp_s32_configure()
290 clk_phase = !!(SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPHA); in spi_nxp_s32_configure()
291 clk_polarity = !!(SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPOL); in spi_nxp_s32_configure()
293 hold_cs = !!(spi_cfg->operation & SPI_HOLD_ON_CS); in spi_nxp_s32_configure()
294 lsb = !!(spi_cfg->operation & SPI_TRANSFER_LSB); in spi_nxp_s32_configure()
296 slave_mode = !!(SPI_OP_MODE_GET(spi_cfg->operation)); in spi_nxp_s32_configure()
297 frame_size = SPI_WORD_SIZE_GET(spi_cfg->operation); in spi_nxp_s32_configure()
298 cs_active_high = !!(spi_cfg->operation & SPI_CS_ACTIVE_HIGH); in spi_nxp_s32_configure()
300 if (slave_mode == (!!(config->spi_hw_cfg->Mcr & SPI_MCR_MSTR_MASK))) { in spi_nxp_s32_configure()
302 return -ENOTSUP; in spi_nxp_s32_configure()
307 return -ENOTSUP; in spi_nxp_s32_configure()
311 LOG_ERR("SPI does not support to shifting out with LSB in slave mode"); in spi_nxp_s32_configure()
312 return -ENOTSUP; in spi_nxp_s32_configure()
315 if (spi_cfg->slave >= config->num_cs) { in spi_nxp_s32_configure()
317 spi_cfg->slave, config->num_cs - 1); in spi_nxp_s32_configure()
318 return -ENOTSUP; in spi_nxp_s32_configure()
323 return -ENOTSUP; in spi_nxp_s32_configure()
326 if ((spi_cfg->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) { in spi_nxp_s32_configure()
328 return -ENOTSUP; in spi_nxp_s32_configure()
331 if (spi_cfg->operation & SPI_MODE_LOOP) { in spi_nxp_s32_configure()
333 return -ENOTSUP; in spi_nxp_s32_configure()
337 LOG_ERR("For CS has active state is high, a GPIO pin must be used to" in spi_nxp_s32_configure()
339 return -ENOTSUP; in spi_nxp_s32_configure()
344 if ((spi_cfg->frequency < SPI_NXP_S32_MIN_FREQ) || in spi_nxp_s32_configure()
345 (spi_cfg->frequency > SPI_NXP_S32_MAX_FREQ)) { in spi_nxp_s32_configure()
347 LOG_ERR("The frequency is out of range"); in spi_nxp_s32_configure()
348 return -ENOTSUP; in spi_nxp_s32_configure()
351 spi_nxp_s32_getbestfreq(clock_rate, spi_cfg->frequency, &best_baud); in spi_nxp_s32_configure()
353 data->transfer_cfg.Ctar &= ~(SPI_CTAR_BR_MASK | SPI_CTAR_PBR_MASK); in spi_nxp_s32_configure()
354 data->transfer_cfg.Ctar |= SPI_CTAR_BR(best_baud.scaler) | in spi_nxp_s32_configure()
357 data->transfer_cfg.PushrCmd &= ~((SPI_PUSHR_CONT_MASK | SPI_PUSHR_PCS_MASK) >> 16U); in spi_nxp_s32_configure()
361 data->transfer_cfg.PushrCmd |= hold_cs << 15U; in spi_nxp_s32_configure()
362 data->transfer_cfg.PushrCmd |= (1U << spi_cfg->slave); in spi_nxp_s32_configure()
366 data->transfer_cfg.Ctar &= ~(SPI_CTAR_CPHA_MASK | SPI_CTAR_CPOL_MASK); in spi_nxp_s32_configure()
367 data->transfer_cfg.Ctar |= SPI_CTAR_CPHA(clk_phase) | SPI_CTAR_CPOL(clk_polarity); in spi_nxp_s32_configure()
369 Spi_Ip_UpdateFrameSize(&data->transfer_cfg, frame_size); in spi_nxp_s32_configure()
370 Spi_Ip_UpdateLsb(&data->transfer_cfg, lsb); in spi_nxp_s32_configure()
372 data->ctx.config = spi_cfg; in spi_nxp_s32_configure()
373 data->bytes_per_frame = SPI_NXP_S32_BYTE_PER_FRAME(frame_size); in spi_nxp_s32_configure()
384 lsb, hold_cs, frame_size, spi_cfg->slave); in spi_nxp_s32_configure()
398 struct spi_nxp_s32_data *data = dev->data; in transceive()
399 struct spi_context *context = &data->ctx; in transceive()
408 return -ENOTSUP; in transceive()
443 spi_context_update_tx(context, 1U, data->transfer_len); in transceive()
444 spi_context_update_rx(context, 1U, data->transfer_len); in transceive()
452 ret = data->ctx.recv_frames; in transceive()
484 struct spi_nxp_s32_data *data = dev->data; in spi_nxp_s32_release()
488 spi_context_unlock_unconditionally(&data->ctx); in spi_nxp_s32_release()
495 const struct spi_nxp_s32_config *config = dev->config; in spi_nxp_s32_init()
496 struct spi_nxp_s32_data *data = dev->data; in spi_nxp_s32_init()
503 if (!device_is_ready(config->clock_dev)) { in spi_nxp_s32_init()
505 return -ENODEV; in spi_nxp_s32_init()
508 ret = clock_control_on(config->clock_dev, config->clock_subsys); in spi_nxp_s32_init()
514 ret = clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_rate); in spi_nxp_s32_init()
520 ret = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT); in spi_nxp_s32_init()
525 if (Spi_Ip_Init(config->spi_hw_cfg)) { in spi_nxp_s32_init()
526 return -EBUSY; in spi_nxp_s32_init()
530 if (Spi_Ip_UpdateTransferMode(config->spi_hw_cfg->Instance, SPI_IP_INTERRUPT)) { in spi_nxp_s32_init()
531 return -EBUSY; in spi_nxp_s32_init()
534 config->irq_config_func(dev); in spi_nxp_s32_init()
541 spi_nxp_s32_getbestdelay(clock_rate, config->sck_cs_delay, &scaler, &prescaler); in spi_nxp_s32_init()
545 spi_nxp_s32_getbestdelay(clock_rate, config->cs_sck_delay, &scaler, &prescaler); in spi_nxp_s32_init()
549 spi_nxp_s32_getbestdelay(clock_rate, config->cs_cs_delay, &scaler, &prescaler); in spi_nxp_s32_init()
553 data->transfer_cfg.Ctar |= ctar; in spi_nxp_s32_init()
554 data->transfer_cfg.DeviceParams = &data->transfer_params; in spi_nxp_s32_init()
556 ret = spi_context_cs_configure_all(&data->ctx); in spi_nxp_s32_init()
561 spi_context_unlock_unconditionally(&data->ctx); in spi_nxp_s32_init()
570 const struct spi_nxp_s32_config *config = dev->config; in spi_nxp_s32_isr()
572 Spi_Ip_IrqHandler(config->spi_hw_cfg->Instance); in spi_nxp_s32_isr()
577 struct spi_nxp_s32_data *data = dev->data; in spi_nxp_s32_transfer_callback()
581 spi_context_update_tx(&data->ctx, 1U, data->transfer_len); in spi_nxp_s32_transfer_callback()
582 spi_context_update_rx(&data->ctx, 1U, data->transfer_len); in spi_nxp_s32_transfer_callback()
584 if (spi_nxp_s32_transfer_done(&data->ctx)) { in spi_nxp_s32_transfer_callback()
585 spi_context_complete(&data->ctx, dev, 0); in spi_nxp_s32_transfer_callback()
586 spi_context_cs_control(&data->ctx, false); in spi_nxp_s32_transfer_callback()
592 ret = -EIO; in spi_nxp_s32_transfer_callback()
596 spi_context_complete(&data->ctx, dev, ret); in spi_nxp_s32_transfer_callback()
597 spi_context_cs_control(&data->ctx, false); in spi_nxp_s32_transfer_callback()
662 * support, all inner module Chip Selects are active low.