18 #include <zephyr/drivers/spi.h>
19 #include <zephyr/drivers/spi/rtio.h>
131 	/* arg holds SPI DMA data  in dma_callback()
191 	blk_cfg->dest_address = ll_func_dma_get_reg_addr(cfg->spi, SPI_STM32_DMA_TX);  in spi_stm32_dma_tx_load()
250 	blk_cfg->source_address = ll_func_dma_get_reg_addr(cfg->spi, SPI_STM32_DMA_RX);  in spi_stm32_dma_rx_load()
313 static void spi_stm32_send_next_frame(SPI_TypeDef *spi,  in spi_stm32_send_next_frame()  argument
323 		LL_SPI_TransmitData8(spi, tx_frame);  in spi_stm32_send_next_frame()
329 		LL_SPI_TransmitData16(spi, tx_frame);  in spi_stm32_send_next_frame()
334 static void spi_stm32_read_next_frame(SPI_TypeDef *spi,  in spi_stm32_read_next_frame()  argument
341 		rx_frame = LL_SPI_ReceiveData8(spi);  in spi_stm32_read_next_frame()
347 		rx_frame = LL_SPI_ReceiveData16(spi);  in spi_stm32_read_next_frame()
360 static int spi_stm32_get_err(SPI_TypeDef *spi)  in spi_stm32_get_err()  argument
362 	uint32_t sr = LL_SPI_ReadReg(spi, SR);  in spi_stm32_get_err()
369 		if (LL_SPI_IsActiveFlag_OVR(spi)) {  in spi_stm32_get_err()
370 			LL_SPI_ClearFlag_OVR(spi);  in spi_stm32_get_err()
379 static void spi_stm32_shift_fifo(SPI_TypeDef *spi, struct spi_stm32_data *data)  in spi_stm32_shift_fifo()  argument
381 	uint32_t transfer_dir = LL_SPI_GetTransferDirection(spi);  in spi_stm32_shift_fifo()
384 		ll_func_rx_is_not_empty(spi)) {  in spi_stm32_shift_fifo()
385 		spi_stm32_read_next_frame(spi, data);  in spi_stm32_shift_fifo()
389 		ll_func_tx_is_not_full(spi)) {  in spi_stm32_shift_fifo()
390 		spi_stm32_send_next_frame(spi, data);  in spi_stm32_shift_fifo()
394 /* Shift a SPI frame as master. */
399 		spi_stm32_shift_fifo(cfg->spi, data);  in spi_stm32_shift_m()
401 		uint32_t transfer_dir = LL_SPI_GetTransferDirection(cfg->spi);  in spi_stm32_shift_m()
404 			while (!ll_func_tx_is_not_full(cfg->spi)) {  in spi_stm32_shift_m()
408 			spi_stm32_send_next_frame(cfg->spi, data);  in spi_stm32_shift_m()
412 			while (!ll_func_rx_is_not_empty(cfg->spi)) {  in spi_stm32_shift_m()
416 			spi_stm32_read_next_frame(cfg->spi, data);  in spi_stm32_shift_m()
421 /* Shift a SPI frame as slave. */
422 static void spi_stm32_shift_s(SPI_TypeDef *spi, struct spi_stm32_data *data)  in spi_stm32_shift_s()  argument
424 	if (ll_func_tx_is_not_full(spi) && spi_context_tx_on(&data->ctx)) {  in spi_stm32_shift_s()
429 			LL_SPI_TransmitData8(spi, tx_frame);  in spi_stm32_shift_s()
433 			LL_SPI_TransmitData16(spi, tx_frame);  in spi_stm32_shift_s()
437 		ll_func_disable_int_tx_empty(spi);  in spi_stm32_shift_s()
440 	if (ll_func_rx_is_not_empty(spi) &&  in spi_stm32_shift_s()
445 			rx_frame = LL_SPI_ReceiveData8(spi);  in spi_stm32_shift_s()
449 			rx_frame = LL_SPI_ReceiveData16(spi);  in spi_stm32_shift_s()
457  * Without a FIFO, we can only shift out one frame's worth of SPI
470 		spi_stm32_shift_s(cfg->spi, data);  in spi_stm32_shift_frames()
473 	return spi_stm32_get_err(cfg->spi);  in spi_stm32_shift_frames()
498 	SPI_TypeDef *spi = cfg->spi;  in spi_stm32_complete()  local
502 	ll_func_disable_int_tx_empty(spi);  in spi_stm32_complete()
503 	ll_func_disable_int_rx_not_empty(spi);  in spi_stm32_complete()
504 	ll_func_disable_int_errors(spi);  in spi_stm32_complete()
508 		LL_SPI_DisableIT_EOT(spi);  in spi_stm32_complete()
517 	while (ll_func_rx_is_not_empty(spi)) {  in spi_stm32_complete()
518 		(void) LL_SPI_ReceiveData8(spi);  in spi_stm32_complete()
522 	if (LL_SPI_GetMode(spi) == LL_SPI_MODE_MASTER) {  in spi_stm32_complete()
523 		while (ll_func_spi_is_busy(spi)) {  in spi_stm32_complete()
531 	if (LL_SPI_IsActiveFlag_MODF(spi)) {  in spi_stm32_complete()
532 		LL_SPI_ClearFlag_MODF(spi);  in spi_stm32_complete()
536 	uint32_t transfer_dir = LL_SPI_GetTransferDirection(spi);  in spi_stm32_complete()
539 		LL_SPI_ClearFlag_TXTF(spi);  in spi_stm32_complete()
540 		LL_SPI_ClearFlag_OVR(spi);  in spi_stm32_complete()
541 		LL_SPI_ClearFlag_EOT(spi);  in spi_stm32_complete()
542 		LL_SPI_SetTransferSize(spi, 0);  in spi_stm32_complete()
544 		LL_SPI_SetTransferSize(spi, 0);  in spi_stm32_complete()
549 		ll_func_disable_spi(spi);  in spi_stm32_complete()
564 	SPI_TypeDef *spi = cfg->spi;  in spi_stm32_isr()  local
567 	/* Some spurious interrupts are triggered when SPI is not enabled; ignore them.  in spi_stm32_isr()
571 		if (!LL_SPI_IsEnabled(spi)) {  in spi_stm32_isr()
576 	err = spi_stm32_get_err(spi);  in spi_stm32_isr()
590 	uint32_t transfer_dir = LL_SPI_GetTransferDirection(spi);  in spi_stm32_isr()
624 	SPI_TypeDef *spi = cfg->spi;  in spi_stm32_configure()  local
631 				LL_SPI_SetTransferDirection(spi, LL_SPI_HALF_DUPLEX_TX);  in spi_stm32_configure()
633 				LL_SPI_SetTransferDirection(spi, LL_SPI_HALF_DUPLEX_RX);  in spi_stm32_configure()
647 		LL_SPI_SetStandard(spi, LL_SPI_PROTOCOL_TI);  in spi_stm32_configure()
655 		LL_SPI_SetStandard(spi, LL_SPI_PROTOCOL_MOTOROLA);  in spi_stm32_configure()
689 	LL_SPI_Disable(spi);  in spi_stm32_configure()
690 	LL_SPI_SetBaudRatePrescaler(spi, scaler[br - 1]);  in spi_stm32_configure()
693 		LL_SPI_SetClockPolarity(spi, LL_SPI_POLARITY_HIGH);  in spi_stm32_configure()
695 		LL_SPI_SetClockPolarity(spi, LL_SPI_POLARITY_LOW);  in spi_stm32_configure()
699 		LL_SPI_SetClockPhase(spi, LL_SPI_PHASE_2EDGE);  in spi_stm32_configure()
701 		LL_SPI_SetClockPhase(spi, LL_SPI_PHASE_1EDGE);  in spi_stm32_configure()
706 			LL_SPI_SetTransferDirection(spi, LL_SPI_HALF_DUPLEX_TX);  in spi_stm32_configure()
708 			LL_SPI_SetTransferDirection(spi, LL_SPI_HALF_DUPLEX_RX);  in spi_stm32_configure()
711 		LL_SPI_SetTransferDirection(spi, LL_SPI_FULL_DUPLEX);  in spi_stm32_configure()
715 		LL_SPI_SetTransferBitOrder(spi, LL_SPI_LSB_FIRST);  in spi_stm32_configure()
717 		LL_SPI_SetTransferBitOrder(spi, LL_SPI_MSB_FIRST);  in spi_stm32_configure()
720 	LL_SPI_DisableCRC(spi);  in spi_stm32_configure()
725 			if (LL_SPI_GetNSSPolarity(spi) == LL_SPI_NSS_POLARITY_LOW)  in spi_stm32_configure()
726 				LL_SPI_SetInternalSSLevel(spi, LL_SPI_SS_LEVEL_HIGH);  in spi_stm32_configure()
729 		LL_SPI_SetNSSMode(spi, LL_SPI_NSS_SOFT);  in spi_stm32_configure()
732 			LL_SPI_SetNSSMode(spi, LL_SPI_NSS_HARD_INPUT);  in spi_stm32_configure()
734 			LL_SPI_SetNSSMode(spi, LL_SPI_NSS_HARD_OUTPUT);  in spi_stm32_configure()
739 		LL_SPI_SetMode(spi, LL_SPI_MODE_SLAVE);  in spi_stm32_configure()
741 		LL_SPI_SetMode(spi, LL_SPI_MODE_MASTER);  in spi_stm32_configure()
745 		LL_SPI_SetDataWidth(spi, LL_SPI_DATAWIDTH_8BIT);  in spi_stm32_configure()
747 		LL_SPI_SetDataWidth(spi, LL_SPI_DATAWIDTH_16BIT);  in spi_stm32_configure()
751 	LL_SPI_SetMasterSSIdleness(spi, cfg->mssi_clocks);  in spi_stm32_configure()
752 	LL_SPI_SetInterDataIdleness(spi, (cfg->midi_clocks << SPI_CFG2_MIDI_Pos));  in spi_stm32_configure()
756 	ll_func_set_fifo_threshold_8bit(spi);  in spi_stm32_configure()
780 	ll_func_disable_spi(cfg->spi);  in spi_stm32_release()
837 	SPI_TypeDef *spi = cfg->spi;  in spi_stm32_half_duplex_switch_to_receive()  local
842 		while (ll_func_spi_is_busy(spi)) {  in spi_stm32_half_duplex_switch_to_receive()
845 		LL_SPI_Disable(spi);  in spi_stm32_half_duplex_switch_to_receive()
859 			LL_SPI_SetTransferSize(spi, (uint32_t) num_bytes / bytes_per_frame);  in spi_stm32_half_duplex_switch_to_receive()
863 		LL_SPI_SetTransferDirection(spi, LL_SPI_HALF_DUPLEX_RX);  in spi_stm32_half_duplex_switch_to_receive()
865 		LL_SPI_Enable(spi);  in spi_stm32_half_duplex_switch_to_receive()
869 		 * if the device is the SPI master,  in spi_stm32_half_duplex_switch_to_receive()
871 		 * LL_SPI_StartMasterTransfer(spi).  in spi_stm32_half_duplex_switch_to_receive()
873 		if (LL_SPI_GetMode(spi) == LL_SPI_MODE_MASTER) {  in spi_stm32_half_duplex_switch_to_receive()
874 			LL_SPI_StartMasterTransfer(spi);  in spi_stm32_half_duplex_switch_to_receive()
875 			while (!LL_SPI_IsActiveMasterTransfer(spi)) {  in spi_stm32_half_duplex_switch_to_receive()
892 			LL_SPI_EnableIT_EOT(spi);  in spi_stm32_half_duplex_switch_to_receive()
896 		ll_func_enable_int_errors(spi);  in spi_stm32_half_duplex_switch_to_receive()
897 		ll_func_enable_int_rx_not_empty(spi);  in spi_stm32_half_duplex_switch_to_receive()
914 	SPI_TypeDef *spi = cfg->spi;  in transceive()  local
943 	uint32_t transfer_dir = LL_SPI_GetTransferDirection(spi);  in transceive()
964 		LL_SPI_SetTransferSize(spi, (uint32_t)total_frames);  in transceive()
969 	LL_SPI_Enable(spi);  in transceive()
973 	 * if the device is the SPI master,  in transceive()
975 	 * LL_SPI_StartMasterTransfer(spi)  in transceive()
977 	if (LL_SPI_GetMode(spi) == LL_SPI_MODE_MASTER) {  in transceive()
978 		LL_SPI_StartMasterTransfer(spi);  in transceive()
979 		while (!LL_SPI_IsActiveMasterTransfer(spi)) {  in transceive()
1000 		LL_SPI_EnableIT_EOT(spi);  in transceive()
1004 	ll_func_enable_int_errors(spi);  in transceive()
1007 		ll_func_enable_int_rx_not_empty(spi);  in transceive()
1010 	ll_func_enable_int_tx_empty(spi);  in transceive()
1018 			transfer_dir = LL_SPI_GetTransferDirection(spi);  in transceive()
1028 			transfer_dir = LL_SPI_GetTransferDirection(spi);  in transceive()
1134 	SPI_TypeDef *spi = cfg->spi;  in transceive_dma()  local
1164 	uint32_t transfer_dir = LL_SPI_GetTransferDirection(spi);  in transceive_dma()
1175 		LL_SPI_SetTransferSize(cfg->spi, frames);  in transceive_dma()
1187 	/* set request before enabling (else SPI CFG1 reg is write protected) */  in transceive_dma()
1189 		LL_SPI_EnableDMAReq_RX(spi);  in transceive_dma()
1190 		LL_SPI_EnableDMAReq_TX(spi);  in transceive_dma()
1192 		LL_SPI_EnableDMAReq_TX(spi);  in transceive_dma()
1194 		LL_SPI_EnableDMAReq_RX(spi);  in transceive_dma()
1197 	LL_SPI_Enable(spi);  in transceive_dma()
1203 		LL_SPI_GetMode(spi) == LL_SPI_MODE_MASTER) {  in transceive_dma()
1204 		LL_SPI_StartMasterTransfer(spi);  in transceive_dma()
1207 	LL_SPI_Enable(spi);  in transceive_dma()
1238 			LL_SPI_GetMode(spi) == LL_SPI_MODE_MASTER) {  in transceive_dma()
1239 			LL_SPI_StartMasterTransfer(spi);  in transceive_dma()
1251 			LL_SPI_EnableDMAReq_RX(spi);  in transceive_dma()
1252 			LL_SPI_EnableDMAReq_TX(spi);  in transceive_dma()
1254 			LL_SPI_EnableDMAReq_TX(spi);  in transceive_dma()
1256 			LL_SPI_EnableDMAReq_RX(spi);  in transceive_dma()
1266 		while (LL_SPI_GetTxFIFOLevel(spi) > 0) {  in transceive_dma()
1271 		WAIT_FOR(ll_func_spi_dma_busy(spi) != 0,  in transceive_dma()
1275 		/* wait until spi is no more busy (spi TX fifo is really empty) */  in transceive_dma()
1276 		while (ll_func_spi_dma_busy(spi) == 0) {  in transceive_dma()
1282 		LL_SPI_DisableDMAReq_TX(spi);  in transceive_dma()
1283 		LL_SPI_DisableDMAReq_RX(spi);  in transceive_dma()
1301 			LL_SPI_Disable(spi);  in transceive_dma()
1302 			LL_SPI_SetTransferDirection(spi, LL_SPI_HALF_DUPLEX_RX);  in transceive_dma()
1314 			LL_SPI_SetTransferSize(cfg->spi, frames);  in transceive_dma()
1316 			LL_SPI_EnableDMAReq_RX(spi);  in transceive_dma()
1319 			LL_SPI_Enable(spi);  in transceive_dma()
1323 	/* spi complete relies on SPI Status Reg which cannot be disabled */  in transceive_dma()
1325 	/* disable spi instance after completion */  in transceive_dma()
1326 	LL_SPI_Disable(spi);  in transceive_dma()
1327 	/* The Config. Reg. on some mcus is write un-protected when SPI is disabled */  in transceive_dma()
1328 	LL_SPI_DisableDMAReq_TX(spi);  in transceive_dma()
1329 	LL_SPI_DisableDMAReq_RX(spi);  in transceive_dma()
1384 static DEVICE_API(spi, api_funcs) = {
1421 		LOG_ERR("Could not enable SPI clock");  in spi_stm32_init()
1430 			LOG_ERR("Could not select SPI domain clock");  in spi_stm32_init()
1439 			LOG_ERR("SPI pinctrl setup failed (%d)", err);  in spi_stm32_init()
1461 	LOG_DBG("SPI with DMA transfer");  in spi_stm32_init()
1497 			LOG_ERR("Could not enable SPI clock");  in spi_stm32_pm_action()
1505 			LOG_ERR("Could not disable SPI clock");  in spi_stm32_pm_action()
1517 				 * "SPI pinctrl sleep state not available"  in spi_stm32_pm_action()
1606 	.spi = (SPI_TypeDef *) DT_INST_REG_ADDR(id),			\