Lines Matching +full:fifo +full:- +full:read +full:- +full:threshold
4 * SPDX-License-Identifier: Apache-2.0
57 #define AMBIQ_SPID_FIFO_LENGTH (AMBIQ_SPID_FIFO_END - AMBIQ_SPID_FIFO_BASE)
67 struct spi_ambiq_data *data = dev->data; in spi_ambiq_reset()
68 struct spi_context *ctx = &data->ctx; in spi_ambiq_reset()
71 am_hal_ios_disable(data->ios_handler); in spi_ambiq_reset()
73 ctx->config = NULL; in spi_ambiq_reset()
75 spi_context_complete(ctx, dev, -ETIMEDOUT); in spi_ambiq_reset()
80 const struct spi_ambiq_config *cfg = dev->config; in spi_ambiq_inform()
82 gpio_pin_set_dt(&cfg->int_gpios, 1); in spi_ambiq_inform()
83 gpio_pin_set_dt(&cfg->int_gpios, 0); in spi_ambiq_inform()
89 struct spi_ambiq_data *data = dev->data; in spi_ambiq_isr()
91 am_hal_ios_interrupt_status_get(data->ios_handler, false, &ui32Status); in spi_ambiq_isr()
92 am_hal_ios_interrupt_clear(data->ios_handler, ui32Status); in spi_ambiq_isr()
94 k_sem_give(&data->spim_wrcmp_sem); in spi_ambiq_isr()
100 struct spi_ambiq_data *data = dev->data; in spi_config()
101 struct spi_context *ctx = &(data->ctx); in spi_config()
104 data->ios_cfg.ui32InterfaceSelect = AM_HAL_IOS_USE_SPI; in spi_config()
111 if (SPI_WORD_SIZE_GET(config->operation) != AMBIQ_SPID_WORD_SIZE) { in spi_config()
113 return -ENOTSUP; in spi_config()
116 if ((config->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) { in spi_config()
118 return -ENOTSUP; in spi_config()
121 if (config->operation & SPI_LOCK_ON) { in spi_config()
123 return -ENOTSUP; in spi_config()
126 if (config->operation & SPI_TRANSFER_LSB) { in spi_config()
128 return -ENOTSUP; in spi_config()
131 if (config->operation & SPI_MODE_CPOL) { in spi_config()
132 if (config->operation & SPI_MODE_CPHA) { in spi_config()
133 data->ios_cfg.ui32InterfaceSelect |= AM_HAL_IOS_SPIMODE_3; in spi_config()
135 data->ios_cfg.ui32InterfaceSelect |= AM_HAL_IOS_SPIMODE_2; in spi_config()
138 if (config->operation & SPI_MODE_CPHA) { in spi_config()
139 data->ios_cfg.ui32InterfaceSelect |= AM_HAL_IOS_SPIMODE_1; in spi_config()
141 data->ios_cfg.ui32InterfaceSelect |= AM_HAL_IOS_SPIMODE_0; in spi_config()
145 if (config->operation & SPI_OP_MODE_MASTER) { in spi_config()
147 return -ENOTSUP; in spi_config()
150 if (config->operation & SPI_MODE_LOOP) { in spi_config()
152 return -ENOTSUP; in spi_config()
157 return -EINVAL; in spi_config()
160 /* Eliminate the "read-only" section, so an external controller can use the in spi_config()
163 data->ios_cfg.ui32ROBase = AMBIQ_SPID_FIFO_BASE; in spi_config()
164 /* Making the "FIFO" section as big as possible. */ in spi_config()
165 data->ios_cfg.ui32FIFOBase = AMBIQ_SPID_FIFO_BASE; in spi_config()
166 /* We don't need any RAM space, so extend the FIFO all the way to the end in spi_config()
169 data->ios_cfg.ui32RAMBase = AMBIQ_SPID_FIFO_END; in spi_config()
170 /* FIFO Threshold - set to half the size */ in spi_config()
171 data->ios_cfg.ui32FIFOThreshold = AMBIQ_SPID_FIFO_LENGTH >> 1; in spi_config()
173 data->ios_cfg.pui8SRAMBuffer = ambiq_spid_sram_buffer, in spi_config()
174 data->ios_cfg.ui32SRAMBufferCap = AMBIQ_SPID_TX_BUFSIZE_MAX, in spi_config()
176 ctx->config = config; in spi_config()
178 ret = am_hal_ios_configure(data->ios_handler, &data->ios_cfg); in spi_config()
185 struct spi_ambiq_data *data = dev->data; in spi_ambiq_xfer()
186 struct spi_context *ctx = &data->ctx; in spi_ambiq_xfer()
194 chunk = (ctx->tx_len > AMBIQ_SPID_TX_BUFSIZE_MAX) in spi_ambiq_xfer()
196 : ctx->tx_len; in spi_ambiq_xfer()
197 am_hal_ios_fifo_space_used(data->ios_handler, &used_space); in spi_ambiq_xfer()
202 if (ctx->tx_buf) { in spi_ambiq_xfer()
203 /* Copy data into FIFO */ in spi_ambiq_xfer()
204 ret = am_hal_ios_fifo_write(data->ios_handler, in spi_ambiq_xfer()
205 (uint8_t *)ctx->tx_buf, chunk, in spi_ambiq_xfer()
211 /* Copy dummy into FIFO */ in spi_ambiq_xfer()
217 data->ios_handler, in spi_ambiq_xfer()
221 chunk -= dummy_written; in spi_ambiq_xfer()
232 (void)k_sem_take(&data->spim_wrcmp_sem, K_FOREVER); in spi_ambiq_xfer()
233 /* Read out the first byte as packet length */ in spi_ambiq_xfer()
243 if (ctx->rx_buf) { in spi_ambiq_xfer()
244 size = MIN(num_read, ctx->rx_len); in spi_ambiq_xfer()
245 /* Read data from LRAM */ in spi_ambiq_xfer()
246 memcpy(ctx->rx_buf, in spi_ambiq_xfer()
254 num_read -= size; in spi_ambiq_xfer()
277 struct spi_ambiq_data *data = dev->data; in spi_ambiq_transceive()
290 spi_context_lock(&data->ctx, false, NULL, NULL, config); in spi_ambiq_transceive()
294 spi_context_release(&data->ctx, ret); in spi_ambiq_transceive()
298 spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1); in spi_ambiq_transceive()
302 spi_context_release(&data->ctx, ret); in spi_ambiq_transceive()
317 struct spi_ambiq_data *data = dev->data; in spi_ambiq_release()
319 if (!spi_context_configured(&data->ctx, config)) { in spi_ambiq_release()
320 return -EINVAL; in spi_ambiq_release()
323 spi_context_unlock_unconditionally(&data->ctx); in spi_ambiq_release()
335 struct spi_ambiq_data *data = dev->data; in spi_ambiq_init()
336 const struct spi_ambiq_config *cfg = dev->config; in spi_ambiq_init()
340 am_hal_ios_initialize((cfg->base - IOSLAVE_BASE) / cfg->size, &data->ios_handler)) { in spi_ambiq_init()
342 return -ENXIO; in spi_ambiq_init()
345 ret = cfg->pwr_func(); in spi_ambiq_init()
347 ret |= pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); in spi_ambiq_init()
355 am_hal_ios_interrupt_clear(data->ios_handler, AM_HAL_IOS_INT_ALL); in spi_ambiq_init()
356 am_hal_ios_interrupt_enable(data->ios_handler, AMBIQ_SPID_INT_ERR | AM_HAL_IOS_INT_IOINTW | in spi_ambiq_init()
358 cfg->irq_config_func(); in spi_ambiq_init()
362 am_hal_ios_uninitialize(data->ios_handler); in spi_ambiq_init()
364 spi_context_unlock_unconditionally(&data->ctx); in spi_ambiq_init()
372 struct spi_ambiq_data *data = dev->data; in spi_ambiq_pm_action()
384 return -ENOTSUP; in spi_ambiq_pm_action()
387 ret = am_hal_ios_power_ctrl(data->ios_handler, status, true); in spi_ambiq_pm_action()
390 return -EPERM; in spi_ambiq_pm_action()