Lines Matching +full:data +full:- +full:pin +full:- +full:start
7 * PCH provides SMBus 2.0 - compliant Host Controller.
9 * SPDX-License-Identifier: Apache-2.0
17 /* Host Configuration (HCFG) - Offset 40h, 8 bits */
46 #define PCH_SMBUS_HCTL_CMD_BYTE_DATA (2 << 2) /* Byte Data cmd */
47 #define PCH_SMBUS_HCTL_CMD_WORD_DATA (3 << 2) /* Word Data cmd */
58 #define PCH_SMBUS_HCTL_START BIT(6) /* Start SMBUS cmd */
69 /* Set 7-bit address */
75 /* Data 0 Register (HD0) */
76 #define PCH_SMBUS_HD0 0x05 /* Data 0 / Count */
78 /* Data 1 Register (HD1) */
79 #define PCH_SMBUS_HD1 0x06 /* Data 1 */
81 /* Host Block Data (HBD) */
82 #define PCH_SMBUS_HBD 0x07 /* Host block data */
84 /* Packet Error Check Data Register (PEC) */
85 #define PCH_SMBUS_PEC 0x08 /* PEC data */
90 /* Slave Data Register (SD) (16 bits) */
91 #define PCH_SMBUS_SD 0x0a /* Slave data */
100 #define PCH_SMBUS_AUXC_EN_32BUF BIT(1) /* Enable 32-byte buf */
102 /* SMLink Pin Control Register (SMLC) */
103 #define PCH_SMBUS_SMLC 0x0e /* SMLink pin control */
105 /* SMBus Pin control Register (SMBC) */
106 #define PCH_SMBUS_SMBC 0x0f /* SMBus pin control */
107 #define PCH_SMBUS_SMBC_CLK_CUR_STS BIT(0) /* SMBCLK pin status */
108 #define PCH_SMBUS_SMBC_DATA_CUR_STS BIT(1) /* SMBDATA pin status */
109 #define PCH_SMBUS_SMBC_CLK_CTL BIT(2) /* SMBCLK pin CTL */
124 /* Notify Data Low Byte Register (NDLB) */
125 #define PCH_SMBUS_NDLB 0x16 /* Notify Data low */
127 /* Notify Data High Byte Register (NDHB) */
128 #define PCH_SMBUS_NDHB 0x17 /* Notify Data high */