182 	uint32_t reg_val = sys_read32(reg_base + XUARTPS_CR_OFFSET);  in xlnx_ps_disable_uart()
206 	uint32_t reg_val = sys_read32(reg_base + XUARTPS_CR_OFFSET);  in xlnx_ps_enable_uart()
304 	reg_val = sys_read32(reg_base + XUARTPS_MR_OFFSET);  in uart_xlnx_ps_init()
346 	uint32_t reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET);  in uart_xlnx_ps_poll_in()
349 		*c = (unsigned char)sys_read32(reg_base + XUARTPS_FIFO_OFFSET);  in uart_xlnx_ps_poll_in()
377 		reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET);  in uart_xlnx_ps_poll_out()
383 		reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET);  in uart_xlnx_ps_poll_out()
609 	mode_reg    = sys_read32(reg_base + XUARTPS_MR_OFFSET);  in uart_xlnx_ps_configure()
610 	modemcr_reg = sys_read32(reg_base + XUARTPS_MODEMCR_OFFSET);  in uart_xlnx_ps_configure()
817 	uint32_t mode_reg    = sys_read32(reg_base + XUARTPS_MR_OFFSET);  in uart_xlnx_ps_config_get()
818 	uint32_t modemcr_reg = sys_read32(reg_base + XUARTPS_MODEMCR_OFFSET);  in uart_xlnx_ps_config_get()
850 		while ((sys_read32(reg_base + XUARTPS_SR_OFFSET) & XUARTPS_SR_TXFULL) != 0) {  in uart_xlnx_ps_fifo_fill()
872 	uint32_t reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET);  in uart_xlnx_ps_fifo_read()
876 		rx_data[inum] = (uint8_t)sys_read32(reg_base  in uart_xlnx_ps_fifo_read()
879 		reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET);  in uart_xlnx_ps_fifo_read()
923 	uint32_t reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET);  in uart_xlnx_ps_irq_tx_ready()
942 	uint32_t reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET);  in uart_xlnx_ps_irq_tx_complete()
985 	uint32_t reg_val = sys_read32(reg_base + XUARTPS_ISR_OFFSET);  in uart_xlnx_ps_irq_rx_ready()
1043 	uint32_t reg_imr = sys_read32(reg_base + XUARTPS_IMR_OFFSET);  in uart_xlnx_ps_irq_is_pending()
1044 	uint32_t reg_isr = sys_read32(reg_base + XUARTPS_ISR_OFFSET);  in uart_xlnx_ps_irq_is_pending()