180 static void xlnx_ps_disable_uart(uintptr_t reg_base)  in xlnx_ps_disable_uart()  argument
182 	uint32_t reg_val = sys_read32(reg_base + XUARTPS_CR_OFFSET);  in xlnx_ps_disable_uart()
187 	sys_write32(reg_val, reg_base + XUARTPS_CR_OFFSET);  in xlnx_ps_disable_uart()
204 static void xlnx_ps_enable_uart(uintptr_t reg_base)  in xlnx_ps_enable_uart()  argument
206 	uint32_t reg_val = sys_read32(reg_base + XUARTPS_CR_OFFSET);  in xlnx_ps_enable_uart()
211 	sys_write32(reg_val, reg_base + XUARTPS_CR_OFFSET);  in xlnx_ps_enable_uart()
233 	uintptr_t reg_base = DEVICE_MMIO_GET(dev);  in set_baudrate()  local
268 		sys_write32(divisor, reg_base + XUARTPS_BAUDDIV_OFFSET);  in set_baudrate()
269 		sys_write32(generator, reg_base + XUARTPS_BAUDGEN_OFFSET);  in set_baudrate()
291 	uintptr_t reg_base = DEVICE_MMIO_GET(dev);  in uart_xlnx_ps_init()  local
294 	xlnx_ps_disable_uart(reg_base);  in uart_xlnx_ps_init()
304 	reg_val = sys_read32(reg_base + XUARTPS_MR_OFFSET);  in uart_xlnx_ps_init()
309 	sys_write32(reg_val, reg_base + XUARTPS_MR_OFFSET);  in uart_xlnx_ps_init()
312 	sys_write32(0x01U, reg_base + XUARTPS_RXWM_OFFSET);  in uart_xlnx_ps_init()
315 	sys_write32(XUARTPS_IXR_MASK, reg_base + XUARTPS_IDR_OFFSET);  in uart_xlnx_ps_init()
323 	sys_write32(XUARTPS_IXR_MASK, reg_base + XUARTPS_ISR_OFFSET);  in uart_xlnx_ps_init()
330 	xlnx_ps_enable_uart(reg_base);  in uart_xlnx_ps_init()
345 	uintptr_t reg_base = DEVICE_MMIO_GET(dev);  in uart_xlnx_ps_poll_in()  local
346 	uint32_t reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET);  in uart_xlnx_ps_poll_in()
349 		*c = (unsigned char)sys_read32(reg_base + XUARTPS_FIFO_OFFSET);  in uart_xlnx_ps_poll_in()
372 	uintptr_t reg_base = DEVICE_MMIO_GET(dev);  in uart_xlnx_ps_poll_out()  local
377 		reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET);  in uart_xlnx_ps_poll_out()
380 	sys_write32((uint32_t)(c & 0xFF), reg_base + XUARTPS_FIFO_OFFSET);  in uart_xlnx_ps_poll_out()
383 		reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET);  in uart_xlnx_ps_poll_out()
604 	uintptr_t reg_base   = DEVICE_MMIO_GET(dev);  in uart_xlnx_ps_configure()  local
609 	mode_reg    = sys_read32(reg_base + XUARTPS_MR_OFFSET);  in uart_xlnx_ps_configure()
610 	modemcr_reg = sys_read32(reg_base + XUARTPS_MODEMCR_OFFSET);  in uart_xlnx_ps_configure()
627 	xlnx_ps_disable_uart(reg_base);  in uart_xlnx_ps_configure()
634 	sys_write32(mode_reg,    reg_base + XUARTPS_MR_OFFSET);  in uart_xlnx_ps_configure()
635 	sys_write32(modemcr_reg, reg_base + XUARTPS_MODEMCR_OFFSET);  in uart_xlnx_ps_configure()
638 	xlnx_ps_enable_uart(reg_base);  in uart_xlnx_ps_configure()
809 	uintptr_t reg_base = DEVICE_MMIO_GET(dev);  in uart_xlnx_ps_config_get()  local
817 	uint32_t mode_reg    = sys_read32(reg_base + XUARTPS_MR_OFFSET);  in uart_xlnx_ps_config_get()
818 	uint32_t modemcr_reg = sys_read32(reg_base + XUARTPS_MODEMCR_OFFSET);  in uart_xlnx_ps_config_get()
845 	uintptr_t reg_base = DEVICE_MMIO_GET(dev);  in uart_xlnx_ps_fifo_fill()  local
848 	sys_write32(XUARTPS_IXR_TXEMPTY, reg_base + XUARTPS_IDR_OFFSET);  in uart_xlnx_ps_fifo_fill()
850 		while ((sys_read32(reg_base + XUARTPS_SR_OFFSET) & XUARTPS_SR_TXFULL) != 0) {  in uart_xlnx_ps_fifo_fill()
852 		sys_write32((uint32_t)tx_data[data_iter++], reg_base + XUARTPS_FIFO_OFFSET);  in uart_xlnx_ps_fifo_fill()
854 	sys_write32(XUARTPS_IXR_TXEMPTY, reg_base + XUARTPS_IER_OFFSET);  in uart_xlnx_ps_fifo_fill()
871 	uintptr_t reg_base = DEVICE_MMIO_GET(dev);  in uart_xlnx_ps_fifo_read()  local
872 	uint32_t reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET);  in uart_xlnx_ps_fifo_read()
876 		rx_data[inum] = (uint8_t)sys_read32(reg_base  in uart_xlnx_ps_fifo_read()
879 		reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET);  in uart_xlnx_ps_fifo_read()
892 	uintptr_t reg_base = DEVICE_MMIO_GET(dev);  in uart_xlnx_ps_irq_tx_enable()  local
896 		reg_base + XUARTPS_IER_OFFSET);  in uart_xlnx_ps_irq_tx_enable()
906 	uintptr_t reg_base = DEVICE_MMIO_GET(dev);  in uart_xlnx_ps_irq_tx_disable()  local
910 		reg_base + XUARTPS_IDR_OFFSET);  in uart_xlnx_ps_irq_tx_disable()
922 	uintptr_t reg_base = DEVICE_MMIO_GET(dev);  in uart_xlnx_ps_irq_tx_ready()  local
923 	uint32_t reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET);  in uart_xlnx_ps_irq_tx_ready()
941 	uintptr_t reg_base = DEVICE_MMIO_GET(dev);  in uart_xlnx_ps_irq_tx_complete()  local
942 	uint32_t reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET);  in uart_xlnx_ps_irq_tx_complete()
958 	uintptr_t reg_base = DEVICE_MMIO_GET(dev);  in uart_xlnx_ps_irq_rx_enable()  local
960 	sys_write32(XUARTPS_IXR_RTRIG, reg_base + XUARTPS_IER_OFFSET);  in uart_xlnx_ps_irq_rx_enable()
970 	uintptr_t reg_base = DEVICE_MMIO_GET(dev);  in uart_xlnx_ps_irq_rx_disable()  local
972 	sys_write32(XUARTPS_IXR_RTRIG, reg_base + XUARTPS_IDR_OFFSET);  in uart_xlnx_ps_irq_rx_disable()
984 	uintptr_t reg_base = DEVICE_MMIO_GET(dev);  in uart_xlnx_ps_irq_rx_ready()  local
985 	uint32_t reg_val = sys_read32(reg_base + XUARTPS_ISR_OFFSET);  in uart_xlnx_ps_irq_rx_ready()
990 		sys_write32(XUARTPS_IXR_RTRIG, reg_base + XUARTPS_ISR_OFFSET);  in uart_xlnx_ps_irq_rx_ready()
1002 	uintptr_t reg_base = DEVICE_MMIO_GET(dev);  in uart_xlnx_ps_irq_err_enable()  local
1010 	    reg_base + XUARTPS_IER_OFFSET);  in uart_xlnx_ps_irq_err_enable()
1022 	uintptr_t reg_base = DEVICE_MMIO_GET(dev);  in uart_xlnx_ps_irq_err_disable()  local
1030 	    reg_base + XUARTPS_IDR_OFFSET);  in uart_xlnx_ps_irq_err_disable()
1042 	uintptr_t reg_base = DEVICE_MMIO_GET(dev);  in uart_xlnx_ps_irq_is_pending()  local
1043 	uint32_t reg_imr = sys_read32(reg_base + XUARTPS_IMR_OFFSET);  in uart_xlnx_ps_irq_is_pending()
1044 	uint32_t reg_isr = sys_read32(reg_base + XUARTPS_ISR_OFFSET);  in uart_xlnx_ps_irq_is_pending()