Lines Matching +full:rx +full:- +full:data +full:- +full:mode
1 /* uart_xlnx_ps.c - Xilinx Zynq family serial driver */
6 * SPDX-License-Identifier: Apache-2.0
19 * - the following macro for the number of bytes between register addresses:
42 * Comp. Xilinx Zynq-7000 Technical Reference Manual (ug585), chap. B.33
47 #define XUARTPS_MR_OFFSET 0x0004U /**< Mode Register [9:0] */
53 #define XUARTPS_RXTOUT_OFFSET 0x001CU /**< RX Timeout [7:0] */
54 #define XUARTPS_RXWM_OFFSET 0x0020U /**< RX FIFO Trigger Level [5:0] */
62 #define XUARTPS_RXBS_OFFSET 0x0048U /**< RX FIFO Byte Status [11:0] */
67 #define XUARTPS_CR_TORST 0x00000040U /**< RX timeout counter restart */
70 #define XUARTPS_CR_RX_DIS 0x00000008U /**< RX disabled. */
71 #define XUARTPS_CR_RX_EN 0x00000004U /**< RX enabled */
74 #define XUARTPS_CR_RXRST 0x00000001U /**< RX logic reset */
76 /* Mode Register Bits Definition */
78 #define XUARTPS_MR_CHMODE_R_LOOP 0x00000300U /**< Remote loopback mode */
79 #define XUARTPS_MR_CHMODE_L_LOOP 0x00000200U /**< Local loopback mode */
80 #define XUARTPS_MR_CHMODE_ECHO 0x00000100U /**< Auto echo mode */
81 #define XUARTPS_MR_CHMODE_NORM 0x00000000U /**< Normal mode */
82 #define XUARTPS_MR_CHMODE_SHIFT 8U /**< Mode shift */
83 #define XUARTPS_MR_CHMODE_MASK 0x00000300U /**< Mode mask */
89 #define XUARTPS_MR_PARITY_NONE 0x00000020U /**< No parity mode */
90 #define XUARTPS_MR_PARITY_MARK 0x00000018U /**< Mark parity mode */
91 #define XUARTPS_MR_PARITY_SPACE 0x00000010U /**< Space parity mode */
92 #define XUARTPS_MR_PARITY_ODD 0x00000008U /**< Odd parity mode */
93 #define XUARTPS_MR_PARITY_EVEN 0x00000000U /**< Even parity mode */
96 #define XUARTPS_MR_CHARLEN_6_BIT 0x00000006U /**< 6 bits data */
97 #define XUARTPS_MR_CHARLEN_7_BIT 0x00000004U /**< 7 bits data */
98 #define XUARTPS_MR_CHARLEN_8_BIT 0x00000000U /**< 8 bits data */
99 #define XUARTPS_MR_CHARLEN_SHIFT 1U /**< Data Length shift */
100 #define XUARTPS_MR_CHARLEN_MASK 0x00000006U /**< Data length mask */
104 #define XUARTPS_IXR_RBRK 0x00002000U /**< Rx FIFO break detect interrupt */
115 #define XUARTPS_IXR_RXFULL 0x00000004U /**< RX FIFO full interrupt. */
116 #define XUARTPS_IXR_RXEMPTY 0x00000002U /**< RX FIFO empty interrupt. */
117 #define XUARTPS_IXR_RTRIG 0x00000001U /**< RX FIFO trigger interrupt. */
130 #define XUARTPS_SR_FLOWDEL 0x00001000U /**< RX FIFO fill over flow delay */
132 #define XUARTPS_SR_RACTIVE 0x00000400U /**< RX active */
135 #define XUARTPS_SR_RXFULL 0x00000004U /**< RX FIFO full */
136 #define XUARTPS_SR_RXEMPTY 0x00000002U /**< RX FIFO empty */
137 #define XUARTPS_SR_RTRIG 0x00000001U /**< RX FIFO fill over trigger */
152 /** Device data structure */
167 * @brief Disables the UART's RX and TX function.
169 * Writes 'Disable RX' and 'Disable TX' command bits into the respective
176 * of the UART are modified at run-time.
191 * @brief Enables the UART's RX and TX function.
193 * Writes 'Enable RX' and 'Enable TX' command bits into the respective
200 * of the UART are being modified at run-time.
222 * registers is described in the Zynq-7000 TRM, chapter 19.2.3 'Baud Rate
230 const struct uart_xlnx_ps_dev_config *dev_cfg = dev->config; in set_baudrate()
231 uint32_t baud = dev_cfg->baud_rate; in set_baudrate()
232 uint32_t clk_freq = dev_cfg->sys_clk_freq; in set_baudrate()
253 bauderr = baud - tmpbaud; in set_baudrate()
255 bauderr = tmpbaud - baud; in set_baudrate()
264 * -> This function is always called from a context in which in set_baudrate()
284 const struct uart_xlnx_ps_dev_config *dev_cfg = dev->config; in uart_xlnx_ps_init()
293 /* Disable RX/TX before changing any configuration data */ in uart_xlnx_ps_init()
297 err = pinctrl_apply_state(dev_cfg->pincfg, PINCTRL_STATE_DEFAULT); in uart_xlnx_ps_init()
311 /* Set RX FIFO trigger at 1 data bytes. */ in uart_xlnx_ps_init()
314 /* Disable all interrupts, polling mode is default */ in uart_xlnx_ps_init()
318 set_baudrate(dev, dev_cfg->baud_rate); in uart_xlnx_ps_init()
326 dev_cfg->irq_config_func(dev); in uart_xlnx_ps_init()
341 * @return 0 if a character arrived, -1 if the input buffer if empty.
352 return -1; in uart_xlnx_ps_poll_in()
357 * @brief Output a character in polled mode.
360 * the data register.
388 * @brief Converts a parity enum value to a Mode Register bit mask.
392 * into a bit mask within the Mode Register.
394 * It is assumed that the Mode Register contents that are being
398 * @param mode_reg Pointer to the Mode Register contents to which
411 * Translate the new parity configuration to the mode register's in uart_xlnx_ps_cfg2ll_parity()
443 * @brief Converts a stop bit enum value to a Mode Register bit mask.
447 * into a bit mask within the Mode Register.
449 * It is assumed that the Mode Register contents that are being
453 * @param mode_reg Pointer to the Mode Register contents to which
465 * Translate the new stop bit configuration to the mode register's in uart_xlnx_ps_cfg2ll_stopbits()
493 * @brief Converts a data bit enum value to a Mode Register bit mask.
496 * framework for the configuration of the UART's data bit setting
497 * into a bit mask within the Mode Register.
499 * It is assumed that the Mode Register contents that are being
503 * @param mode_reg Pointer to the Mode Register contents to which
504 * the data bit configuration shall be added.
508 * data bit configuration being provided by the caller.
515 * Translate the new data bit configuration to the mode register's in uart_xlnx_ps_cfg2ll_databits()
517 * 0xb : 8 data bits in uart_xlnx_ps_cfg2ll_databits()
518 * 10b : 7 data bits in uart_xlnx_ps_cfg2ll_databits()
519 * 11b : 6 data bits in uart_xlnx_ps_cfg2ll_databits()
525 /* Controller doesn't support 5 or 9 data bits */ in uart_xlnx_ps_cfg2ll_databits()
587 * @brief Configures the UART device at run-time.
589 * Configures the UART device at run-time according to the
590 * configuration data provided by the caller.
602 (struct uart_xlnx_ps_dev_config *)dev->config; in uart_xlnx_ps_configure()
608 /* Read the current mode register & modem control register values */ in uart_xlnx_ps_configure()
612 /* Mask out all items that might be re-configured */ in uart_xlnx_ps_configure()
619 if ((!uart_xlnx_ps_cfg2ll_parity(&mode_reg, cfg->parity)) || in uart_xlnx_ps_configure()
620 (!uart_xlnx_ps_cfg2ll_stopbits(&mode_reg, cfg->stop_bits)) || in uart_xlnx_ps_configure()
621 (!uart_xlnx_ps_cfg2ll_databits(&mode_reg, cfg->data_bits)) || in uart_xlnx_ps_configure()
622 (!uart_xlnx_ps_cfg2ll_hwctrl(&modemcr_reg, cfg->flow_ctrl))) { in uart_xlnx_ps_configure()
623 return -ENOTSUP; in uart_xlnx_ps_configure()
630 set_baudrate(dev, cfg->baudrate); in uart_xlnx_ps_configure()
631 dev_cfg->baud_rate = cfg->baudrate; in uart_xlnx_ps_configure()
637 /* Re-enable the controller */ in uart_xlnx_ps_configure()
645 * @brief Converts a Mode Register bit mask to a parity configuration
649 * the UART's Mode Register into a value of an enumeration type provided
652 * @param mode_reg The current Mode Register contents from which the
662 * Obtain the current parity configuration from the mode register's in uart_xlnx_ps_ll2cfg_parity()
664 * 000b : even -> reset value in uart_xlnx_ps_ll2cfg_parity()
687 * @brief Converts a Mode Register bit mask to a stop bit configuration
691 * the UART's Mode Register into a value of an enumeration type provided
694 * @param mode_reg The current Mode Register contents from which the
704 * Obtain the current stop bit configuration from the mode register's in uart_xlnx_ps_ll2cfg_stopbits()
706 * 00b : 1 stop bit -> reset value in uart_xlnx_ps_ll2cfg_stopbits()
724 * @brief Converts a Mode Register bit mask to a data bit configuration
727 * Converts a bit mask representing the UART's data bit setting within
728 * the UART's Mode Register into a value of an enumeration type provided
731 * @param mode_reg The current Mode Register contents from which the
732 * data bit setting shall be extracted.
734 * @return The current data bit setting mapped to the UART driver API's
741 * Obtain the current data bit configuration from the mode register's in uart_xlnx_ps_ll2cfg_databits()
743 * 0xb : 8 data bits -> reset value in uart_xlnx_ps_ll2cfg_databits()
744 * 10b : 7 data bits in uart_xlnx_ps_ll2cfg_databits()
745 * 11b : 6 data bits in uart_xlnx_ps_ll2cfg_databits()
779 * 0b : no flow control -> reset value in uart_xlnx_ps_ll2cfg_hwctrl()
793 * @brief Returns the current configuration of the UART at run-time.
795 * Returns the current configuration of the UART at run-time by obtaining
796 * the current configuration from the UART's Mode and Modem Control Registers
800 * @param cfg Pointer to the data structure to which the current configuration
808 const struct uart_xlnx_ps_dev_config *dev_cfg = dev->config; in uart_xlnx_ps_config_get()
812 * Read the Mode & Modem control registers - they contain in uart_xlnx_ps_config_get()
813 * the current data / stop bit and parity settings (Mode in uart_xlnx_ps_config_get()
820 cfg->baudrate = dev_cfg->baud_rate; in uart_xlnx_ps_config_get()
821 cfg->parity = uart_xlnx_ps_ll2cfg_parity(mode_reg); in uart_xlnx_ps_config_get()
822 cfg->stop_bits = uart_xlnx_ps_ll2cfg_stopbits(mode_reg); in uart_xlnx_ps_config_get()
823 cfg->data_bits = uart_xlnx_ps_ll2cfg_databits(mode_reg); in uart_xlnx_ps_config_get()
824 cfg->flow_ctrl = uart_xlnx_ps_ll2cfg_hwctrl(modemcr_reg); in uart_xlnx_ps_config_get()
833 * @brief Fill FIFO with data
836 * @param tx_data Data to transmit
849 while (size--) { in uart_xlnx_ps_fifo_fill()
860 * @brief Read data from FIFO
863 * @param rxData Data container
952 * @brief Enable RX interrupt in IER
964 * @brief Disable RX interrupt in IER
976 * @brief Check if Rx IRQ has been raised
1076 struct uart_xlnx_ps_dev_data_t *dev_data = dev->data; in uart_xlnx_ps_irq_callback_set()
1078 dev_data->user_cb = cb; in uart_xlnx_ps_irq_callback_set()
1079 dev_data->user_data = cb_data; in uart_xlnx_ps_irq_callback_set()
1091 const struct uart_xlnx_ps_dev_data_t *data = dev->data; in uart_xlnx_ps_isr() local
1093 if (data->user_cb) { in uart_xlnx_ps_isr()
1094 data->user_cb(dev, data->user_data); in uart_xlnx_ps_isr()