Lines Matching refs:dma_rx
1111 LOG_DBG("rx_rdy: (%d %d)", data->dma_rx.offset, data->dma_rx.counter); in async_evt_rx_rdy()
1115 .data.rx.buf = data->dma_rx.buffer, in async_evt_rx_rdy()
1116 .data.rx.len = data->dma_rx.counter - data->dma_rx.offset, in async_evt_rx_rdy()
1117 .data.rx.offset = data->dma_rx.offset in async_evt_rx_rdy()
1121 data->dma_rx.offset = data->dma_rx.counter; in async_evt_rx_rdy()
1136 .data.rx_stop.data.len = data->dma_rx.counter, in async_evt_rx_err()
1138 .data.rx_stop.data.buf = data->dma_rx.buffer in async_evt_rx_err()
1191 .data.rx_buf.buf = data->dma_rx.buffer, in async_evt_rx_buf_release()
1212 if (dma_get_status(data->dma_rx.dma_dev, in uart_stm32_dma_rx_flush()
1213 data->dma_rx.dma_channel, &stat) == 0) { in uart_stm32_dma_rx_flush()
1214 size_t rx_rcv_len = data->dma_rx.buffer_length - in uart_stm32_dma_rx_flush()
1216 if (rx_rcv_len > data->dma_rx.offset) { in uart_stm32_dma_rx_flush()
1217 data->dma_rx.counter = rx_rcv_len; in uart_stm32_dma_rx_flush()
1271 if (data->dma_rx.timeout == 0) { in uart_stm32_isr()
1275 async_timer_start(&data->dma_rx.timeout_work, in uart_stm32_isr()
1276 data->dma_rx.timeout); in uart_stm32_isr()
1394 data->dma_rx.enabled = true; in uart_stm32_dma_rx_enable()
1401 data->dma_rx.enabled = false; in uart_stm32_dma_rx_disable()
1413 if (!data->dma_rx.enabled) { in uart_stm32_async_rx_disable()
1426 (void)k_work_cancel_delayable(&data->dma_rx.timeout_work); in uart_stm32_async_rx_disable()
1428 dma_stop(data->dma_rx.dma_dev, data->dma_rx.dma_channel); in uart_stm32_async_rx_disable()
1485 data->dma_rx.offset = 0; in uart_stm32_dma_replace_buffer()
1486 data->dma_rx.counter = 0; in uart_stm32_dma_replace_buffer()
1487 data->dma_rx.buffer = data->rx_next_buffer; in uart_stm32_dma_replace_buffer()
1488 data->dma_rx.buffer_length = data->rx_next_buffer_len; in uart_stm32_dma_replace_buffer()
1489 data->dma_rx.blk_cfg.block_size = data->dma_rx.buffer_length; in uart_stm32_dma_replace_buffer()
1490 data->dma_rx.blk_cfg.dest_address = (uint32_t)data->dma_rx.buffer; in uart_stm32_dma_replace_buffer()
1494 dma_reload(data->dma_rx.dma_dev, data->dma_rx.dma_channel, in uart_stm32_dma_replace_buffer()
1495 data->dma_rx.blk_cfg.source_address, in uart_stm32_dma_replace_buffer()
1496 data->dma_rx.blk_cfg.dest_address, in uart_stm32_dma_replace_buffer()
1497 data->dma_rx.blk_cfg.block_size); in uart_stm32_dma_replace_buffer()
1499 dma_start(data->dma_rx.dma_dev, data->dma_rx.dma_channel); in uart_stm32_dma_replace_buffer()
1518 (void)k_work_cancel_delayable(&data->dma_rx.timeout_work); in uart_stm32_dma_rx_cb()
1521 data->dma_rx.counter = data->dma_rx.buffer_length; in uart_stm32_dma_rx_cb()
1540 k_work_reschedule(&data->dma_rx.timeout_work, K_TICKS(1)); in uart_stm32_dma_rx_cb()
1619 if (data->dma_rx.dma_dev == NULL) { in uart_stm32_async_rx_enable()
1623 if (data->dma_rx.enabled) { in uart_stm32_async_rx_enable()
1635 data->dma_rx.offset = 0; in uart_stm32_async_rx_enable()
1636 data->dma_rx.buffer = rx_buf; in uart_stm32_async_rx_enable()
1637 data->dma_rx.buffer_length = buf_size; in uart_stm32_async_rx_enable()
1638 data->dma_rx.counter = 0; in uart_stm32_async_rx_enable()
1639 data->dma_rx.timeout = timeout; in uart_stm32_async_rx_enable()
1644 data->dma_rx.blk_cfg.block_size = buf_size; in uart_stm32_async_rx_enable()
1645 data->dma_rx.blk_cfg.dest_address = (uint32_t)data->dma_rx.buffer; in uart_stm32_async_rx_enable()
1647 ret = dma_config(data->dma_rx.dma_dev, data->dma_rx.dma_channel, in uart_stm32_async_rx_enable()
1648 &data->dma_rx.dma_cfg); in uart_stm32_async_rx_enable()
1655 if (dma_start(data->dma_rx.dma_dev, data->dma_rx.dma_channel)) { in uart_stm32_async_rx_enable()
1717 struct uart_stm32_data, dma_rx); in uart_stm32_async_rx_timeout()
1722 if (data->dma_rx.counter == data->dma_rx.buffer_length) { in uart_stm32_async_rx_timeout()
1756 } else if (!data->dma_rx.enabled) { in uart_stm32_async_rx_buf_rsp()
1782 if (data->dma_rx.dma_dev != NULL) { in uart_stm32_async_init()
1783 if (!device_is_ready(data->dma_rx.dma_dev)) { in uart_stm32_async_init()
1798 k_work_init_delayable(&data->dma_rx.timeout_work, in uart_stm32_async_init()
1804 memset(&data->dma_rx.blk_cfg, 0, sizeof(data->dma_rx.blk_cfg)); in uart_stm32_async_init()
1810 data->dma_rx.blk_cfg.source_address = in uart_stm32_async_init()
1813 data->dma_rx.blk_cfg.source_address = in uart_stm32_async_init()
1818 data->dma_rx.blk_cfg.dest_address = 0; /* dest not ready */ in uart_stm32_async_init()
1820 if (data->dma_rx.src_addr_increment) { in uart_stm32_async_init()
1821 data->dma_rx.blk_cfg.source_addr_adj = DMA_ADDR_ADJ_INCREMENT; in uart_stm32_async_init()
1823 data->dma_rx.blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in uart_stm32_async_init()
1826 if (data->dma_rx.dst_addr_increment) { in uart_stm32_async_init()
1827 data->dma_rx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT; in uart_stm32_async_init()
1829 data->dma_rx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in uart_stm32_async_init()
1833 data->dma_rx.blk_cfg.source_reload_en = 0; in uart_stm32_async_init()
1834 data->dma_rx.blk_cfg.dest_reload_en = 0; in uart_stm32_async_init()
1835 data->dma_rx.blk_cfg.fifo_mode_control = data->dma_rx.fifo_threshold; in uart_stm32_async_init()
1837 data->dma_rx.dma_cfg.head_block = &data->dma_rx.blk_cfg; in uart_stm32_async_init()
1838 data->dma_rx.dma_cfg.user_data = (void *)dev; in uart_stm32_async_init()