Lines Matching +full:fixed +full:- +full:baudrate
2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
6 * SPDX-License-Identifier: Apache-2.0
43 #include <zephyr/linker/linker-defs.h>
45 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
70 /* Placeholder value when wakeup-line DT property is not defined */
105 struct uart_stm32_data *data = dev->data; in uart_stm32_pm_policy_state_lock_get()
107 if (!data->pm_policy_state_on) { in uart_stm32_pm_policy_state_lock_get()
108 data->pm_policy_state_on = true; in uart_stm32_pm_policy_state_lock_get()
118 struct uart_stm32_data *data = dev->data; in uart_stm32_pm_policy_state_lock_put()
120 if (data->pm_policy_state_on) { in uart_stm32_pm_policy_state_lock_put()
121 data->pm_policy_state_on = false; in uart_stm32_pm_policy_state_lock_put()
132 const struct uart_stm32_config *config = dev->config; in uart_stm32_set_baudrate()
133 USART_TypeDef *usart = config->usart; in uart_stm32_set_baudrate()
134 struct uart_stm32_data *data = dev->data; in uart_stm32_set_baudrate()
139 if (IS_ENABLED(STM32_UART_DOMAIN_CLOCK_SUPPORT) && (config->pclk_len > 1)) { in uart_stm32_set_baudrate()
140 if (clock_control_get_rate(data->clock, in uart_stm32_set_baudrate()
141 (clock_control_subsys_t)&config->pclken[1], in uart_stm32_set_baudrate()
147 if (clock_control_get_rate(data->clock, in uart_stm32_set_baudrate()
148 (clock_control_subsys_t)&config->pclken[0], in uart_stm32_set_baudrate()
170 LOG_ERR("Unable to set %s to %d", dev->name, baud_rate); in uart_stm32_set_baudrate()
180 LOG_ERR("Unable to set %s to %d", dev->name, baud_rate); in uart_stm32_set_baudrate()
224 const struct uart_stm32_config *config = dev->config; in uart_stm32_set_parity()
226 LL_USART_SetParity(config->usart, parity); in uart_stm32_set_parity()
231 const struct uart_stm32_config *config = dev->config; in uart_stm32_get_parity()
233 return LL_USART_GetParity(config->usart); in uart_stm32_get_parity()
239 const struct uart_stm32_config *config = dev->config; in uart_stm32_set_stopbits()
241 LL_USART_SetStopBitsLength(config->usart, stopbits); in uart_stm32_set_stopbits()
246 const struct uart_stm32_config *config = dev->config; in uart_stm32_get_stopbits()
248 return LL_USART_GetStopBitsLength(config->usart); in uart_stm32_get_stopbits()
254 const struct uart_stm32_config *config = dev->config; in uart_stm32_set_databits()
256 LL_USART_SetDataWidth(config->usart, databits); in uart_stm32_set_databits()
261 const struct uart_stm32_config *config = dev->config; in uart_stm32_get_databits()
263 return LL_USART_GetDataWidth(config->usart); in uart_stm32_get_databits()
269 const struct uart_stm32_config *config = dev->config; in uart_stm32_set_hwctrl()
271 LL_USART_SetHWFlowCtrl(config->usart, hwctrl); in uart_stm32_set_hwctrl()
276 const struct uart_stm32_config *config = dev->config; in uart_stm32_get_hwctrl()
278 return LL_USART_GetHWFlowCtrl(config->usart); in uart_stm32_get_hwctrl()
285 const struct uart_stm32_config *config = dev->config; in uart_stm32_set_driver_enable()
288 LL_USART_EnableDEMode(config->usart); in uart_stm32_set_driver_enable()
290 LL_USART_DisableDEMode(config->usart); in uart_stm32_set_driver_enable()
296 const struct uart_stm32_config *config = dev->config; in uart_stm32_get_driver_enable()
298 return LL_USART_IsEnabledDEMode(config->usart); in uart_stm32_get_driver_enable()
336 if (IS_LPUART_INSTANCE(config->usart)) { in uart_stm32_cfg2ll_stopbits()
349 if (IS_LPUART_INSTANCE(config->usart)) { in uart_stm32_cfg2ll_stopbits()
482 const struct uart_stm32_config *config = dev->config; in uart_stm32_parameters_set()
483 struct uart_stm32_data *data = dev->data; in uart_stm32_parameters_set()
484 struct uart_config *uart_cfg = data->uart_cfg; in uart_stm32_parameters_set()
485 const uint32_t parity = uart_stm32_cfg2ll_parity(cfg->parity); in uart_stm32_parameters_set()
486 const uint32_t stopbits = uart_stm32_cfg2ll_stopbits(config, cfg->stop_bits); in uart_stm32_parameters_set()
487 const uint32_t databits = uart_stm32_cfg2ll_databits(cfg->data_bits, in uart_stm32_parameters_set()
488 cfg->parity); in uart_stm32_parameters_set()
489 const uint32_t flowctrl = uart_stm32_cfg2ll_hwctrl(cfg->flow_ctrl); in uart_stm32_parameters_set()
491 bool driver_enable = cfg->flow_ctrl == UART_CFG_FLOW_CTRL_RS485; in uart_stm32_parameters_set()
495 /* Called via (re-)init function, so the SoC either just booted, in uart_stm32_parameters_set()
496 * or is returning from a low-power state where it lost register in uart_stm32_parameters_set()
499 LL_USART_ConfigCharacter(config->usart, in uart_stm32_parameters_set()
504 uart_stm32_set_baudrate(dev, cfg->baudrate); in uart_stm32_parameters_set()
529 if (cfg->baudrate != uart_cfg->baudrate) { in uart_stm32_parameters_set()
530 uart_stm32_set_baudrate(dev, cfg->baudrate); in uart_stm32_parameters_set()
531 uart_cfg->baudrate = cfg->baudrate; in uart_stm32_parameters_set()
540 const struct uart_stm32_config *config = dev->config; in uart_stm32_configure()
541 USART_TypeDef *usart = config->usart; in uart_stm32_configure()
542 struct uart_stm32_data *data = dev->data; in uart_stm32_configure()
543 struct uart_config *uart_cfg = data->uart_cfg; in uart_stm32_configure()
544 const uint32_t parity = uart_stm32_cfg2ll_parity(cfg->parity); in uart_stm32_configure()
545 const uint32_t stopbits = uart_stm32_cfg2ll_stopbits(config, cfg->stop_bits); in uart_stm32_configure()
546 const uint32_t databits = uart_stm32_cfg2ll_databits(cfg->data_bits, in uart_stm32_configure()
547 cfg->parity); in uart_stm32_configure()
550 if ((cfg->parity == UART_CFG_PARITY_MARK) || in uart_stm32_configure()
551 (cfg->parity == UART_CFG_PARITY_SPACE)) { in uart_stm32_configure()
552 return -ENOTSUP; in uart_stm32_configure()
556 if ((cfg->parity != UART_CFG_PARITY_NONE) && in uart_stm32_configure()
557 (cfg->data_bits == UART_CFG_DATA_BITS_9)) { in uart_stm32_configure()
558 return -ENOTSUP; in uart_stm32_configure()
564 if (uart_stm32_ll2cfg_stopbits(stopbits) != cfg->stop_bits) { in uart_stm32_configure()
565 return -ENOTSUP; in uart_stm32_configure()
571 if (uart_stm32_ll2cfg_databits(databits, parity) != cfg->data_bits) { in uart_stm32_configure()
572 return -ENOTSUP; in uart_stm32_configure()
576 if (!(cfg->flow_ctrl == UART_CFG_FLOW_CTRL_NONE in uart_stm32_configure()
577 || (cfg->flow_ctrl == UART_CFG_FLOW_CTRL_RTS_CTS && in uart_stm32_configure()
580 || (cfg->flow_ctrl == UART_CFG_FLOW_CTRL_RS485 && in uart_stm32_configure()
584 return -ENOTSUP; in uart_stm32_configure()
589 /* Set basic parameters, such as data-/stop-bit, parity, and baudrate */ in uart_stm32_configure()
594 /* Upon successful configuration, persist the syscall-passed in uart_stm32_configure()
596 * This allows restoring it, should the device return from a low-power in uart_stm32_configure()
607 struct uart_stm32_data *data = dev->data; in uart_stm32_config_get()
608 struct uart_config *uart_cfg = data->uart_cfg; in uart_stm32_config_get()
610 cfg->baudrate = uart_cfg->baudrate; in uart_stm32_config_get()
611 cfg->parity = uart_stm32_ll2cfg_parity(uart_stm32_get_parity(dev)); in uart_stm32_config_get()
612 cfg->stop_bits = uart_stm32_ll2cfg_stopbits( in uart_stm32_config_get()
614 cfg->data_bits = uart_stm32_ll2cfg_databits( in uart_stm32_config_get()
616 cfg->flow_ctrl = uart_stm32_ll2cfg_hwctrl( in uart_stm32_config_get()
620 cfg->flow_ctrl = UART_CFG_FLOW_CTRL_RS485; in uart_stm32_config_get()
633 const struct uart_stm32_config *config = dev->config; in uart_stm32_poll_in_visitor()
634 USART_TypeDef *usart = config->usart; in uart_stm32_poll_in_visitor()
646 return -1; in uart_stm32_poll_in_visitor()
659 const struct uart_stm32_config *config = dev->config; in uart_stm32_poll_out_visitor()
660 USART_TypeDef *usart = config->usart; in uart_stm32_poll_out_visitor()
662 struct uart_stm32_data *data = dev->data; in uart_stm32_poll_out_visitor()
686 if (!data->tx_poll_stream_on && !data->tx_int_stream_on) { in uart_stm32_poll_out_visitor()
687 data->tx_poll_stream_on = true; in uart_stm32_poll_out_visitor()
751 const struct uart_stm32_config *config = dev->config; in uart_stm32_err_check()
752 USART_TypeDef *usart = config->usart; in uart_stm32_err_check()
788 * --> so is the RXNE flag also cleared ! in uart_stm32_err_check()
811 struct uart_stm32_data *data = dev->data; in __uart_stm32_get_clock()
814 data->clock = clk; in __uart_stm32_get_clock()
824 const struct uart_stm32_config *config = dev->config; in uart_stm32_fifo_fill_visitor()
825 USART_TypeDef *usart = config->usart; in uart_stm32_fifo_fill_visitor()
836 while ((size - num_tx > 0) && LL_USART_IsActiveFlag_TXE(usart)) { in uart_stm32_fifo_fill_visitor()
860 return -ENOTSUP; in uart_stm32_fifo_fill()
871 const struct uart_stm32_config *config = dev->config; in uart_stm32_fifo_read_visitor()
872 USART_TypeDef *usart = config->usart; in uart_stm32_fifo_read_visitor()
875 while ((size - num_rx > 0) && LL_USART_IsActiveFlag_RXNE(usart)) { in uart_stm32_fifo_read_visitor()
905 return -ENOTSUP; in uart_stm32_fifo_read()
925 return -ENOTSUP; in uart_stm32_fifo_fill_u16()
942 return -ENOTSUP; in uart_stm32_fifo_read_u16()
952 const struct uart_stm32_config *config = dev->config; in uart_stm32_irq_tx_enable()
954 struct uart_stm32_data *data = dev->data; in uart_stm32_irq_tx_enable()
960 data->tx_poll_stream_on = false; in uart_stm32_irq_tx_enable()
961 data->tx_int_stream_on = true; in uart_stm32_irq_tx_enable()
964 LL_USART_EnableIT_TC(config->usart); in uart_stm32_irq_tx_enable()
973 const struct uart_stm32_config *config = dev->config; in uart_stm32_irq_tx_disable()
975 struct uart_stm32_data *data = dev->data; in uart_stm32_irq_tx_disable()
981 LL_USART_DisableIT_TC(config->usart); in uart_stm32_irq_tx_disable()
984 data->tx_int_stream_on = false; in uart_stm32_irq_tx_disable()
995 const struct uart_stm32_config *config = dev->config; in uart_stm32_irq_tx_ready()
997 return LL_USART_IsActiveFlag_TXE(config->usart) && in uart_stm32_irq_tx_ready()
998 LL_USART_IsEnabledIT_TC(config->usart); in uart_stm32_irq_tx_ready()
1003 const struct uart_stm32_config *config = dev->config; in uart_stm32_irq_tx_complete()
1005 return LL_USART_IsActiveFlag_TC(config->usart); in uart_stm32_irq_tx_complete()
1010 const struct uart_stm32_config *config = dev->config; in uart_stm32_irq_rx_enable()
1012 LL_USART_EnableIT_RXNE(config->usart); in uart_stm32_irq_rx_enable()
1017 const struct uart_stm32_config *config = dev->config; in uart_stm32_irq_rx_disable()
1019 LL_USART_DisableIT_RXNE(config->usart); in uart_stm32_irq_rx_disable()
1024 const struct uart_stm32_config *config = dev->config; in uart_stm32_irq_rx_ready()
1029 return LL_USART_IsActiveFlag_RXNE(config->usart); in uart_stm32_irq_rx_ready()
1034 const struct uart_stm32_config *config = dev->config; in uart_stm32_irq_err_enable()
1035 USART_TypeDef *usart = config->usart; in uart_stm32_irq_err_enable()
1051 const struct uart_stm32_config *config = dev->config; in uart_stm32_irq_err_disable()
1052 USART_TypeDef *usart = config->usart; in uart_stm32_irq_err_disable()
1068 const struct uart_stm32_config *config = dev->config; in uart_stm32_irq_is_pending()
1069 USART_TypeDef *usart = config->usart; in uart_stm32_irq_is_pending()
1086 struct uart_stm32_data *data = dev->data; in uart_stm32_irq_callback_set()
1088 data->user_cb = cb; in uart_stm32_irq_callback_set()
1089 data->user_data = cb_data; in uart_stm32_irq_callback_set()
1092 data->async_cb = NULL; in uart_stm32_irq_callback_set()
1093 data->async_user_data = NULL; in uart_stm32_irq_callback_set()
1104 if (data->async_cb) { in async_user_callback()
1105 data->async_cb(data->uart_dev, event, data->async_user_data); in async_user_callback()
1111 LOG_DBG("rx_rdy: (%d %d)", data->dma_rx.offset, data->dma_rx.counter); in async_evt_rx_rdy()
1115 .data.rx.buf = data->dma_rx.buffer, in async_evt_rx_rdy()
1116 .data.rx.len = data->dma_rx.counter - data->dma_rx.offset, in async_evt_rx_rdy()
1117 .data.rx.offset = data->dma_rx.offset in async_evt_rx_rdy()
1121 data->dma_rx.offset = data->dma_rx.counter; in async_evt_rx_rdy()
1136 .data.rx_stop.data.len = data->dma_rx.counter, in async_evt_rx_err()
1138 .data.rx_stop.data.buf = data->dma_rx.buffer in async_evt_rx_err()
1146 LOG_DBG("tx done: %d", data->dma_tx.counter); in async_evt_tx_done()
1150 .data.tx.buf = data->dma_tx.buffer, in async_evt_tx_done()
1151 .data.tx.len = data->dma_tx.counter in async_evt_tx_done()
1155 data->dma_tx.buffer_length = 0; in async_evt_tx_done()
1156 data->dma_tx.counter = 0; in async_evt_tx_done()
1163 LOG_DBG("tx abort: %d", data->dma_tx.counter); in async_evt_tx_abort()
1167 .data.tx.buf = data->dma_tx.buffer, in async_evt_tx_abort()
1168 .data.tx.len = data->dma_tx.counter in async_evt_tx_abort()
1172 data->dma_tx.buffer_length = 0; in async_evt_tx_abort()
1173 data->dma_tx.counter = 0; in async_evt_tx_abort()
1191 .data.rx_buf.buf = data->dma_rx.buffer, in async_evt_rx_buf_release()
1210 struct uart_stm32_data *data = dev->data; in uart_stm32_dma_rx_flush()
1212 if (dma_get_status(data->dma_rx.dma_dev, in uart_stm32_dma_rx_flush()
1213 data->dma_rx.dma_channel, &stat) == 0) { in uart_stm32_dma_rx_flush()
1214 size_t rx_rcv_len = data->dma_rx.buffer_length - in uart_stm32_dma_rx_flush()
1216 if (rx_rcv_len > data->dma_rx.offset) { in uart_stm32_dma_rx_flush()
1217 data->dma_rx.counter = rx_rcv_len; in uart_stm32_dma_rx_flush()
1232 struct uart_stm32_data *data = dev->data; in uart_stm32_isr()
1234 const struct uart_stm32_config *config = dev->config; in uart_stm32_isr()
1235 USART_TypeDef *usart = config->usart; in uart_stm32_isr()
1242 if (data->tx_poll_stream_on) { in uart_stm32_isr()
1247 data->tx_poll_stream_on = false; in uart_stm32_isr()
1258 if (data->user_cb) { in uart_stm32_isr()
1259 data->user_cb(dev, data->user_data); in uart_stm32_isr()
1271 if (data->dma_rx.timeout == 0) { in uart_stm32_isr()
1275 async_timer_start(&data->dma_rx.timeout_work, in uart_stm32_isr()
1276 data->dma_rx.timeout); in uart_stm32_isr()
1327 ((buf + len_bytes - 1) <= ((uintptr_t)_nocache_ram_end)); in buf_in_nocache()
1340 ((buf + len_bytes - 1) <= ((uintptr_t)__rodata_region_end)); in buf_in_nocache()
1350 struct uart_stm32_data *data = dev->data; in uart_stm32_async_callback_set()
1352 data->async_cb = callback; in uart_stm32_async_callback_set()
1353 data->async_user_data = user_data; in uart_stm32_async_callback_set()
1356 data->user_cb = NULL; in uart_stm32_async_callback_set()
1357 data->user_data = NULL; in uart_stm32_async_callback_set()
1365 const struct uart_stm32_config *config = dev->config; in uart_stm32_dma_tx_enable()
1367 LL_USART_EnableDMAReq_TX(config->usart); in uart_stm32_dma_tx_enable()
1381 const struct uart_stm32_config *config = dev->config; in uart_stm32_dma_tx_disable()
1383 LL_USART_DisableDMAReq_TX(config->usart); in uart_stm32_dma_tx_disable()
1389 const struct uart_stm32_config *config = dev->config; in uart_stm32_dma_rx_enable()
1390 struct uart_stm32_data *data = dev->data; in uart_stm32_dma_rx_enable()
1392 LL_USART_EnableDMAReq_RX(config->usart); in uart_stm32_dma_rx_enable()
1394 data->dma_rx.enabled = true; in uart_stm32_dma_rx_enable()
1399 struct uart_stm32_data *data = dev->data; in uart_stm32_dma_rx_disable()
1401 data->dma_rx.enabled = false; in uart_stm32_dma_rx_disable()
1406 const struct uart_stm32_config *config = dev->config; in uart_stm32_async_rx_disable()
1407 USART_TypeDef *usart = config->usart; in uart_stm32_async_rx_disable()
1408 struct uart_stm32_data *data = dev->data; in uart_stm32_async_rx_disable()
1413 if (!data->dma_rx.enabled) { in uart_stm32_async_rx_disable()
1415 return -EFAULT; in uart_stm32_async_rx_disable()
1426 (void)k_work_cancel_delayable(&data->dma_rx.timeout_work); in uart_stm32_async_rx_disable()
1428 dma_stop(data->dma_rx.dma_dev, data->dma_rx.dma_channel); in uart_stm32_async_rx_disable()
1430 if (data->rx_next_buffer) { in uart_stm32_async_rx_disable()
1433 .data.rx_buf.buf = data->rx_next_buffer, in uart_stm32_async_rx_disable()
1438 data->rx_next_buffer = NULL; in uart_stm32_async_rx_disable()
1439 data->rx_next_buffer_len = 0; in uart_stm32_async_rx_disable()
1455 struct uart_stm32_data *data = uart_dev->data; in uart_stm32_dma_tx_cb()
1462 (void)k_work_cancel_delayable(&data->dma_tx.timeout_work); in uart_stm32_dma_tx_cb()
1464 if (!dma_get_status(data->dma_tx.dma_dev, in uart_stm32_dma_tx_cb()
1465 data->dma_tx.dma_channel, &stat)) { in uart_stm32_dma_tx_cb()
1466 data->dma_tx.counter = data->dma_tx.buffer_length - in uart_stm32_dma_tx_cb()
1470 data->dma_tx.buffer_length = 0; in uart_stm32_dma_tx_cb()
1477 const struct uart_stm32_config *config = dev->config; in uart_stm32_dma_replace_buffer()
1478 USART_TypeDef *usart = config->usart; in uart_stm32_dma_replace_buffer()
1479 struct uart_stm32_data *data = dev->data; in uart_stm32_dma_replace_buffer()
1482 LOG_DBG("Replacing RX buffer: %d", data->rx_next_buffer_len); in uart_stm32_dma_replace_buffer()
1485 data->dma_rx.offset = 0; in uart_stm32_dma_replace_buffer()
1486 data->dma_rx.counter = 0; in uart_stm32_dma_replace_buffer()
1487 data->dma_rx.buffer = data->rx_next_buffer; in uart_stm32_dma_replace_buffer()
1488 data->dma_rx.buffer_length = data->rx_next_buffer_len; in uart_stm32_dma_replace_buffer()
1489 data->dma_rx.blk_cfg.block_size = data->dma_rx.buffer_length; in uart_stm32_dma_replace_buffer()
1490 data->dma_rx.blk_cfg.dest_address = (uint32_t)data->dma_rx.buffer; in uart_stm32_dma_replace_buffer()
1491 data->rx_next_buffer = NULL; in uart_stm32_dma_replace_buffer()
1492 data->rx_next_buffer_len = 0; in uart_stm32_dma_replace_buffer()
1494 dma_reload(data->dma_rx.dma_dev, data->dma_rx.dma_channel, in uart_stm32_dma_replace_buffer()
1495 data->dma_rx.blk_cfg.source_address, in uart_stm32_dma_replace_buffer()
1496 data->dma_rx.blk_cfg.dest_address, in uart_stm32_dma_replace_buffer()
1497 data->dma_rx.blk_cfg.block_size); in uart_stm32_dma_replace_buffer()
1499 dma_start(data->dma_rx.dma_dev, data->dma_rx.dma_channel); in uart_stm32_dma_replace_buffer()
1511 struct uart_stm32_data *data = uart_dev->data; in uart_stm32_dma_rx_cb()
1518 (void)k_work_cancel_delayable(&data->dma_rx.timeout_work); in uart_stm32_dma_rx_cb()
1521 data->dma_rx.counter = data->dma_rx.buffer_length; in uart_stm32_dma_rx_cb()
1525 if (data->rx_next_buffer != NULL) { in uart_stm32_dma_rx_cb()
1540 k_work_reschedule(&data->dma_rx.timeout_work, K_TICKS(1)); in uart_stm32_dma_rx_cb()
1547 const struct uart_stm32_config *config = dev->config; in uart_stm32_async_tx()
1548 USART_TypeDef *usart = config->usart; in uart_stm32_async_tx()
1549 struct uart_stm32_data *data = dev->data; in uart_stm32_async_tx()
1552 if (data->dma_tx.dma_dev == NULL) { in uart_stm32_async_tx()
1553 return -ENODEV; in uart_stm32_async_tx()
1556 if (data->dma_tx.buffer_length != 0) { in uart_stm32_async_tx()
1557 return -EBUSY; in uart_stm32_async_tx()
1563 return -EFAULT; in uart_stm32_async_tx()
1567 data->dma_tx.buffer = (uint8_t *)tx_data; in uart_stm32_async_tx()
1568 data->dma_tx.buffer_length = buf_size; in uart_stm32_async_tx()
1569 data->dma_tx.timeout = timeout; in uart_stm32_async_tx()
1571 LOG_DBG("tx: l=%d", data->dma_tx.buffer_length); in uart_stm32_async_tx()
1580 data->dma_tx.blk_cfg.source_address = (uint32_t)data->dma_tx.buffer; in uart_stm32_async_tx()
1581 data->dma_tx.blk_cfg.block_size = data->dma_tx.buffer_length; in uart_stm32_async_tx()
1583 ret = dma_config(data->dma_tx.dma_dev, data->dma_tx.dma_channel, in uart_stm32_async_tx()
1584 &data->dma_tx.dma_cfg); in uart_stm32_async_tx()
1588 return -EINVAL; in uart_stm32_async_tx()
1591 if (dma_start(data->dma_tx.dma_dev, data->dma_tx.dma_channel)) { in uart_stm32_async_tx()
1593 return -EFAULT; in uart_stm32_async_tx()
1597 async_timer_start(&data->dma_tx.timeout_work, data->dma_tx.timeout); in uart_stm32_async_tx()
1614 const struct uart_stm32_config *config = dev->config; in uart_stm32_async_rx_enable()
1615 USART_TypeDef *usart = config->usart; in uart_stm32_async_rx_enable()
1616 struct uart_stm32_data *data = dev->data; in uart_stm32_async_rx_enable()
1619 if (data->dma_rx.dma_dev == NULL) { in uart_stm32_async_rx_enable()
1620 return -ENODEV; in uart_stm32_async_rx_enable()
1623 if (data->dma_rx.enabled) { in uart_stm32_async_rx_enable()
1625 return -EBUSY; in uart_stm32_async_rx_enable()
1631 return -EFAULT; in uart_stm32_async_rx_enable()
1635 data->dma_rx.offset = 0; in uart_stm32_async_rx_enable()
1636 data->dma_rx.buffer = rx_buf; in uart_stm32_async_rx_enable()
1637 data->dma_rx.buffer_length = buf_size; in uart_stm32_async_rx_enable()
1638 data->dma_rx.counter = 0; in uart_stm32_async_rx_enable()
1639 data->dma_rx.timeout = timeout; in uart_stm32_async_rx_enable()
1644 data->dma_rx.blk_cfg.block_size = buf_size; in uart_stm32_async_rx_enable()
1645 data->dma_rx.blk_cfg.dest_address = (uint32_t)data->dma_rx.buffer; in uart_stm32_async_rx_enable()
1647 ret = dma_config(data->dma_rx.dma_dev, data->dma_rx.dma_channel, in uart_stm32_async_rx_enable()
1648 &data->dma_rx.dma_cfg); in uart_stm32_async_rx_enable()
1652 return -EINVAL; in uart_stm32_async_rx_enable()
1655 if (dma_start(data->dma_rx.dma_dev, data->dma_rx.dma_channel)) { in uart_stm32_async_rx_enable()
1657 return -EFAULT; in uart_stm32_async_rx_enable()
1688 struct uart_stm32_data *data = dev->data; in uart_stm32_async_tx_abort()
1689 size_t tx_buffer_length = data->dma_tx.buffer_length; in uart_stm32_async_tx_abort()
1693 return -EFAULT; in uart_stm32_async_tx_abort()
1696 (void)k_work_cancel_delayable(&data->dma_tx.timeout_work); in uart_stm32_async_tx_abort()
1697 if (!dma_get_status(data->dma_tx.dma_dev, in uart_stm32_async_tx_abort()
1698 data->dma_tx.dma_channel, &stat)) { in uart_stm32_async_tx_abort()
1699 data->dma_tx.counter = tx_buffer_length - stat.pending_length; in uart_stm32_async_tx_abort()
1703 dma_suspend(data->dma_tx.dma_dev, data->dma_tx.dma_channel); in uart_stm32_async_tx_abort()
1705 dma_stop(data->dma_tx.dma_dev, data->dma_tx.dma_channel); in uart_stm32_async_tx_abort()
1718 const struct device *dev = data->uart_dev; in uart_stm32_async_rx_timeout()
1722 if (data->dma_rx.counter == data->dma_rx.buffer_length) { in uart_stm32_async_rx_timeout()
1736 const struct device *dev = data->uart_dev; in uart_stm32_async_tx_timeout()
1746 struct uart_stm32_data *data = dev->data; in uart_stm32_async_rx_buf_rsp()
1754 if (data->rx_next_buffer != NULL) { in uart_stm32_async_rx_buf_rsp()
1755 err = -EBUSY; in uart_stm32_async_rx_buf_rsp()
1756 } else if (!data->dma_rx.enabled) { in uart_stm32_async_rx_buf_rsp()
1757 err = -EACCES; in uart_stm32_async_rx_buf_rsp()
1762 return -EFAULT; in uart_stm32_async_rx_buf_rsp()
1765 data->rx_next_buffer = buf; in uart_stm32_async_rx_buf_rsp()
1766 data->rx_next_buffer_len = len; in uart_stm32_async_rx_buf_rsp()
1776 const struct uart_stm32_config *config = dev->config; in uart_stm32_async_init()
1777 USART_TypeDef *usart = config->usart; in uart_stm32_async_init()
1778 struct uart_stm32_data *data = dev->data; in uart_stm32_async_init()
1780 data->uart_dev = dev; in uart_stm32_async_init()
1782 if (data->dma_rx.dma_dev != NULL) { in uart_stm32_async_init()
1783 if (!device_is_ready(data->dma_rx.dma_dev)) { in uart_stm32_async_init()
1784 return -ENODEV; in uart_stm32_async_init()
1788 if (data->dma_tx.dma_dev != NULL) { in uart_stm32_async_init()
1789 if (!device_is_ready(data->dma_tx.dma_dev)) { in uart_stm32_async_init()
1790 return -ENODEV; in uart_stm32_async_init()
1798 k_work_init_delayable(&data->dma_rx.timeout_work, in uart_stm32_async_init()
1800 k_work_init_delayable(&data->dma_tx.timeout_work, in uart_stm32_async_init()
1804 memset(&data->dma_rx.blk_cfg, 0, sizeof(data->dma_rx.blk_cfg)); in uart_stm32_async_init()
1810 data->dma_rx.blk_cfg.source_address = in uart_stm32_async_init()
1813 data->dma_rx.blk_cfg.source_address = in uart_stm32_async_init()
1818 data->dma_rx.blk_cfg.dest_address = 0; /* dest not ready */ in uart_stm32_async_init()
1820 if (data->dma_rx.src_addr_increment) { in uart_stm32_async_init()
1821 data->dma_rx.blk_cfg.source_addr_adj = DMA_ADDR_ADJ_INCREMENT; in uart_stm32_async_init()
1823 data->dma_rx.blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in uart_stm32_async_init()
1826 if (data->dma_rx.dst_addr_increment) { in uart_stm32_async_init()
1827 data->dma_rx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT; in uart_stm32_async_init()
1829 data->dma_rx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in uart_stm32_async_init()
1833 data->dma_rx.blk_cfg.source_reload_en = 0; in uart_stm32_async_init()
1834 data->dma_rx.blk_cfg.dest_reload_en = 0; in uart_stm32_async_init()
1835 data->dma_rx.blk_cfg.fifo_mode_control = data->dma_rx.fifo_threshold; in uart_stm32_async_init()
1837 data->dma_rx.dma_cfg.head_block = &data->dma_rx.blk_cfg; in uart_stm32_async_init()
1838 data->dma_rx.dma_cfg.user_data = (void *)dev; in uart_stm32_async_init()
1839 data->rx_next_buffer = NULL; in uart_stm32_async_init()
1840 data->rx_next_buffer_len = 0; in uart_stm32_async_init()
1843 memset(&data->dma_tx.blk_cfg, 0, sizeof(data->dma_tx.blk_cfg)); in uart_stm32_async_init()
1849 data->dma_tx.blk_cfg.dest_address = in uart_stm32_async_init()
1852 data->dma_tx.blk_cfg.dest_address = in uart_stm32_async_init()
1857 data->dma_tx.blk_cfg.source_address = 0; /* not ready */ in uart_stm32_async_init()
1859 if (data->dma_tx.src_addr_increment) { in uart_stm32_async_init()
1860 data->dma_tx.blk_cfg.source_addr_adj = DMA_ADDR_ADJ_INCREMENT; in uart_stm32_async_init()
1862 data->dma_tx.blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in uart_stm32_async_init()
1865 if (data->dma_tx.dst_addr_increment) { in uart_stm32_async_init()
1866 data->dma_tx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT; in uart_stm32_async_init()
1868 data->dma_tx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in uart_stm32_async_init()
1871 data->dma_tx.blk_cfg.fifo_mode_control = data->dma_tx.fifo_threshold; in uart_stm32_async_init()
1873 data->dma_tx.dma_cfg.head_block = &data->dma_tx.blk_cfg; in uart_stm32_async_init()
1874 data->dma_tx.dma_cfg.user_data = (void *)dev; in uart_stm32_async_init()
1951 const struct uart_stm32_config *config = dev->config; in uart_stm32_clocks_enable()
1952 struct uart_stm32_data *data = dev->data; in uart_stm32_clocks_enable()
1957 if (!device_is_ready(data->clock)) { in uart_stm32_clocks_enable()
1959 return -ENODEV; in uart_stm32_clocks_enable()
1963 err = clock_control_on(data->clock, (clock_control_subsys_t)&config->pclken[0]); in uart_stm32_clocks_enable()
1969 if (IS_ENABLED(STM32_UART_DOMAIN_CLOCK_SUPPORT) && (config->pclk_len > 1)) { in uart_stm32_clocks_enable()
1971 (clock_control_subsys_t) &config->pclken[1], in uart_stm32_clocks_enable()
1984 const struct uart_stm32_config *config = dev->config; in uart_stm32_registers_configure()
1985 USART_TypeDef *usart = config->usart; in uart_stm32_registers_configure()
1986 struct uart_stm32_data *data = dev->data; in uart_stm32_registers_configure()
1987 struct uart_config *uart_cfg = data->uart_cfg; in uart_stm32_registers_configure()
1991 if (!device_is_ready(config->reset.dev)) { in uart_stm32_registers_configure()
1993 return -ENODEV; in uart_stm32_registers_configure()
1997 (void)reset_line_toggle_dt(&config->reset); in uart_stm32_registers_configure()
2002 /* Set basic parameters, such as data-/stop-bit, parity, and baudrate */ in uart_stm32_registers_configure()
2005 /* Enable the single wire / half-duplex mode */ in uart_stm32_registers_configure()
2006 if (config->single_wire) { in uart_stm32_registers_configure()
2011 if (config->tx_rx_swap) { in uart_stm32_registers_configure()
2017 if (config->rx_invert) { in uart_stm32_registers_configure()
2023 if (config->tx_invert) { in uart_stm32_registers_configure()
2029 if (config->de_enable) { in uart_stm32_registers_configure()
2031 LOG_ERR("%s does not support driver enable", dev->name); in uart_stm32_registers_configure()
2032 return -EINVAL; in uart_stm32_registers_configure()
2036 LL_USART_SetDEAssertionTime(usart, config->de_assert_time); in uart_stm32_registers_configure()
2037 LL_USART_SetDEDeassertionTime(usart, config->de_deassert_time); in uart_stm32_registers_configure()
2039 if (config->de_invert) { in uart_stm32_registers_configure()
2046 if (config->fifo_enable) { in uart_stm32_registers_configure()
2052 if (config->wakeup_source) { in uart_stm32_registers_configure()
2065 if (config->wakeup_line != STM32_WAKEUP_LINE_NONE) { in uart_stm32_registers_configure()
2067 LL_EXTI_EnableIT_0_31(BIT(config->wakeup_line)); in uart_stm32_registers_configure()
2101 const struct uart_stm32_config *config = dev->config; in uart_stm32_init()
2110 err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); in uart_stm32_init()
2123 config->irq_config_func(dev); in uart_stm32_init()
2136 const struct uart_stm32_config *config = dev->config; in uart_stm32_suspend_setup()
2137 USART_TypeDef *usart = config->usart; in uart_stm32_suspend_setup()
2140 /* Make sure that no USART transfer is on-going */ in uart_stm32_suspend_setup()
2158 const struct uart_stm32_config *config = dev->config; in uart_stm32_pm_action()
2159 struct uart_stm32_data *data = dev->data; in uart_stm32_pm_action()
2166 err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); in uart_stm32_pm_action()
2172 err = clock_control_on(data->clock, in uart_stm32_pm_action()
2173 (clock_control_subsys_t)&config->pclken[0]); in uart_stm32_pm_action()
2180 (!LL_USART_IsEnabled(config->usart))) { in uart_stm32_pm_action()
2190 /* Stop device clock. Note: fixed clocks are not handled yet. */ in uart_stm32_pm_action()
2191 err = clock_control_off(data->clock, (clock_control_subsys_t)&config->pclken[0]); in uart_stm32_pm_action()
2198 err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP); in uart_stm32_pm_action()
2199 if ((err < 0) && (err != -ENOENT)) { in uart_stm32_pm_action()
2201 * If returning -ENOENT, no pins where defined for sleep mode : in uart_stm32_pm_action()
2211 return -ENOTSUP; in uart_stm32_pm_action()
2411 .baudrate = DT_INST_PROP_OR(index, current_speed, \