Lines Matching +full:zephyr +full:- +full:base
4 * SPDX-License-Identifier: Apache-2.0
8 #include "zephyr/spinlock.h"
9 #include "zephyr/sys/printk.h"
10 #include <zephyr/drivers/uart.h>
11 #include <zephyr/drivers/pinctrl.h>
12 #include <zephyr/sys/util.h>
13 #include <zephyr/irq.h>
15 #include <zephyr/logging/log.h>
23 mm_reg_t base; member
39 if (!dev || !dev->config || !dev->data) { in rzt2m_poll_in()
40 return -ENODEV; in rzt2m_poll_in()
43 const struct rzt2m_device_config *config = dev->config; in rzt2m_poll_in()
44 struct rzt2m_device_data *data = dev->data; in rzt2m_poll_in()
46 k_spinlock_key_t key = k_spin_lock(&data->lock); in rzt2m_poll_in()
48 if (FRSR_R(*FRSR(config->base)) == 0) { in rzt2m_poll_in()
49 k_spin_unlock(&data->lock, key); in rzt2m_poll_in()
50 return -1; in rzt2m_poll_in()
52 *c = *RDR(config->base) & RDR_MASK_RDAT; in rzt2m_poll_in()
53 *CFCLR(config->base) |= CFCLR_MASK_RDRFC; in rzt2m_poll_in()
55 if (FRSR_R(*FRSR(config->base)) == 0) { in rzt2m_poll_in()
56 *FFCLR(config->base) |= FFCLR_MASK_DRC; in rzt2m_poll_in()
59 k_spin_unlock(&data->lock, key); in rzt2m_poll_in()
65 if (!dev || !dev->config || !dev->data) { in rzt2m_poll_out()
69 const struct rzt2m_device_config *config = dev->config; in rzt2m_poll_out()
70 struct rzt2m_device_data *data = dev->data; in rzt2m_poll_out()
72 k_spinlock_key_t key = k_spin_lock(&data->lock); in rzt2m_poll_out()
74 int fifo_count = FTSR_T(*FTSR(config->base)); in rzt2m_poll_out()
77 fifo_count = FTSR_T(*FTSR(config->base)); in rzt2m_poll_out()
80 *TDR(config->base) = c; in rzt2m_poll_out()
83 *CFCLR(config->base) |= CFCLR_MASK_TDREC; in rzt2m_poll_out()
85 k_spin_unlock(&data->lock, key); in rzt2m_poll_out()
90 const struct rzt2m_device_config *config = dev->config; in rzt2m_err_check()
92 uint32_t status = *CSR(config->base); in rzt2m_err_check()
113 struct rzt2m_device_data *data = dev->data; in rzt2m_fifo_fill()
114 const struct rzt2m_device_config *config = dev->config; in rzt2m_fifo_fill()
116 k_spinlock_key_t key = k_spin_lock(&data->lock); in rzt2m_fifo_fill()
118 while ((size - num_tx > 0) && uart_rzt2m_irq_tx_ready(dev)) { in rzt2m_fifo_fill()
119 *TDR(config->base) = (uint8_t)tx_data[num_tx++]; in rzt2m_fifo_fill()
122 k_spin_unlock(&data->lock, key); in rzt2m_fifo_fill()
128 struct rzt2m_device_data *data = dev->data; in rzt2m_fifo_read()
129 const struct rzt2m_device_config *config = dev->config; in rzt2m_fifo_read()
131 k_spinlock_key_t key = k_spin_lock(&data->lock); in rzt2m_fifo_read()
133 while (num_rx < size && (FRSR_R(*FRSR(config->base)))) { in rzt2m_fifo_read()
134 rx_data[num_rx++] = *RDR(config->base); in rzt2m_fifo_read()
136 *CFCLR(config->base) = CFCLR_MASK_RDRFC; in rzt2m_fifo_read()
137 *FFCLR(config->base) = FFCLR_MASK_DRC; in rzt2m_fifo_read()
138 k_spin_unlock(&data->lock, key); in rzt2m_fifo_read()
144 const struct rzt2m_device_config *config = dev->config; in uart_rzt2m_irq_rx_enable()
145 *CCR0(config->base) |= CCR0_MASK_RIE | CCR0_MASK_RE; in uart_rzt2m_irq_rx_enable()
150 const struct rzt2m_device_config *config = dev->config; in uart_rzt2m_irq_rx_disable()
151 *CCR0(config->base) &= ~CCR0_MASK_RIE; in uart_rzt2m_irq_rx_disable()
156 const struct rzt2m_device_config *config = dev->config; in uart_rzt2m_irq_tx_enable()
158 *CCR0(config->base) |= CCR0_MASK_TE | CCR0_MASK_TIE | CCR0_MASK_TEIE; in uart_rzt2m_irq_tx_enable()
163 const struct rzt2m_device_config *config = dev->config; in uart_rzt2m_irq_tx_disable()
164 *CCR0(config->base) &= ~(CCR0_MASK_TIE | CCR0_MASK_TEIE); in uart_rzt2m_irq_tx_disable()
169 const struct rzt2m_device_config *config = dev->config; in uart_rzt2m_irq_tx_ready()
171 if (FTSR_T(*FTSR(config->base)) == MAX_FIFO_DEPTH || in uart_rzt2m_irq_tx_ready()
172 ((*CCR0(config->base) & CCR0_MASK_TIE) == 0)) { in uart_rzt2m_irq_tx_ready()
181 const struct rzt2m_device_config *config = dev->config; in uart_rzt2m_irq_rx_ready()
183 if (FRSR_R(*FRSR(config->base))) { in uart_rzt2m_irq_rx_ready()
192 const struct rzt2m_device_config *config = dev->config; in uart_rzt2m_irq_is_pending()
194 if ((*CSR(config->base) & (CSR_MASK_RDRF)) || (*FRSR(config->base) & FRSR_MASK_DR)) { in uart_rzt2m_irq_is_pending()
203 struct rzt2m_device_data *data = dev->data; in uart_rzt2m_irq_callback_set()
205 data->callback = cb; in uart_rzt2m_irq_callback_set()
206 data->callback_data = cb_data; in uart_rzt2m_irq_callback_set()
211 const struct rzt2m_device_config *config = dev->config; in uart_rzt2m_irq_update()
213 *CFCLR(config->base) = CFCLR_MASK_RDRFC; in uart_rzt2m_irq_update()
214 *FFCLR(config->base) = FFCLR_MASK_DRC; in uart_rzt2m_irq_update()
240 if (!dev || !dev->config || !dev->data) { in rzt2m_module_start()
241 return -ENODEV; in rzt2m_module_start()
244 const struct rzt2m_device_config *config = dev->config; in rzt2m_module_start()
245 struct rzt2m_device_data *data = dev->data; in rzt2m_module_start()
246 int interface_id = BASE_TO_IFACE_ID(config->base); in rzt2m_module_start()
250 k_spinlock_key_t key = k_spin_lock(&data->lock); in rzt2m_module_start()
253 /* Dummy-read at least one time as stated in 8.3.1 of the User's Manual: Hardware */ in rzt2m_module_start()
258 return -ENOTSUP; in rzt2m_module_start()
261 /* Dummy-read at least five times as stated in 8.3.1 of the User's Manual: Hardware */ in rzt2m_module_start()
262 dummy = *RDR(config->base); in rzt2m_module_start()
263 dummy = *RDR(config->base); in rzt2m_module_start()
264 dummy = *RDR(config->base); in rzt2m_module_start()
265 dummy = *RDR(config->base); in rzt2m_module_start()
266 dummy = *RDR(config->base); in rzt2m_module_start()
268 k_spin_unlock(&data->lock, key); in rzt2m_module_start()
275 const struct rzt2m_device_config *config = dev->config; in rzt2m_uart_init()
276 struct rzt2m_device_data *data = dev->data; in rzt2m_uart_init()
293 *CCR0(config->base) = CCR0_DEFAULT_VALUE; in rzt2m_uart_init()
294 while (*CCR0(config->base) & (CCR0_MASK_RE | CCR0_MASK_TE)) { in rzt2m_uart_init()
297 *CCR1(config->base) = CCR1_DEFAULT_VALUE; in rzt2m_uart_init()
298 *CCR2(config->base) = CCR2_DEFAULT_VALUE; in rzt2m_uart_init()
299 *CCR3(config->base) = CCR3_DEFAULT_VALUE; in rzt2m_uart_init()
300 *CCR4(config->base) = CCR4_DEFAULT_VALUE; in rzt2m_uart_init()
303 ret = pinctrl_apply_state(config->pin_config, PINCTRL_STATE_DEFAULT); in rzt2m_uart_init()
308 *CFCLR(config->base) = CFCLR_ALL_FLAG_CLEAR; in rzt2m_uart_init()
309 *FFCLR(config->base) = FFCLR_MASK_DRC; in rzt2m_uart_init()
312 *CCR3(config->base) |= (CCR3_MASK_FM); in rzt2m_uart_init()
314 switch (data->uart_cfg.stop_bits) { in rzt2m_uart_init()
319 *CCR3(config->base) |= CCR3_MASK_STP; in rzt2m_uart_init()
322 LOG_ERR("Selected bit stop length is not supported: %u.", data->uart_cfg.stop_bits); in rzt2m_uart_init()
323 return -ENOTSUP; in rzt2m_uart_init()
326 switch (data->uart_cfg.data_bits) { in rzt2m_uart_init()
328 *CCR3(config->base) |= CCR3_CHR_7BIT; in rzt2m_uart_init()
331 *CCR3(config->base) |= CCR3_CHR_8BIT; in rzt2m_uart_init()
335 data->uart_cfg.data_bits); in rzt2m_uart_init()
336 return -ENOTSUP; in rzt2m_uart_init()
339 if (data->uart_cfg.baudrate > ARRAY_SIZE(baud_settings)) { in rzt2m_uart_init()
340 LOG_ERR("Selected baudrate variant is not supported: %u.", data->uart_cfg.baudrate); in rzt2m_uart_init()
341 return -ENOTSUP; in rzt2m_uart_init()
343 baud_setting = baud_settings[data->uart_cfg.baudrate]; in rzt2m_uart_init()
345 *CCR2(config->base) &= ~(CCR2_MASK_BAUD_SETTING); in rzt2m_uart_init()
346 *CCR2(config->base) |= (baud_setting & CCR2_MASK_BAUD_SETTING); in rzt2m_uart_init()
348 *CCR1(config->base) |= (CCR1_MASK_NFEN | CCR1_MASK_SPB2DT | CCR1_MASK_SPB2IO); in rzt2m_uart_init()
350 switch (data->uart_cfg.parity) { in rzt2m_uart_init()
355 *CCR1(config->base) |= CCR1_MASK_PE; in rzt2m_uart_init()
358 *CCR1(config->base) |= (CCR1_MASK_PE | CCR1_MASK_PM); in rzt2m_uart_init()
361 LOG_ERR("Unsupported parity: %u", data->uart_cfg.parity); in rzt2m_uart_init()
365 *FCR(config->base) = FCR_MASK_TFRST | FCR_MASK_RFRST | FCR_TTRG_15 | FCR_RTRG_15; in rzt2m_uart_init()
368 *CCR3(config->base) &= ~CCR3_MASK_CKE; in rzt2m_uart_init()
369 *CCR3(config->base) |= CCR3_CKE_ENABLE; in rzt2m_uart_init()
372 *CFCLR(config->base) = CFCLR_ALL_FLAG_CLEAR; in rzt2m_uart_init()
373 *FFCLR(config->base) = FFCLR_MASK_DRC; in rzt2m_uart_init()
376 config->irq_config_func(dev); in rzt2m_uart_init()
380 *CCR0(config->base) |= (CCR0_MASK_TE | CCR0_MASK_RE); in rzt2m_uart_init()
381 while (!(*CCR0(config->base) & CCR0_MASK_RE)) { in rzt2m_uart_init()
383 while (!(*CCR0(config->base) & CCR0_MASK_TE)) { in rzt2m_uart_init()
394 const struct rzt2m_device_config *config = dev->config; in uart_rzt2m_isr()
396 struct rzt2m_device_data *data = dev->data; in uart_rzt2m_isr()
398 if (data->callback) { in uart_rzt2m_isr()
399 data->callback(dev, data->callback_data); in uart_rzt2m_isr()
403 *CFCLR(config->base) = CFCLR_MASK_RDRFC; in uart_rzt2m_isr()
404 *FFCLR(config->base) = FFCLR_MASK_DRC; in uart_rzt2m_isr()
439 .base = DT_INST_REG_ADDR(n), \