Lines Matching +full:rx +full:- +full:dtc
3 * SPDX-License-Identifier: Apache-2.0
46 /* RX */
80 const struct uart_ra_sci_b_config *cfg = dev->config; in uart_ra_sci_b_poll_in()
83 if (IS_ENABLED(CONFIG_UART_ASYNC_API) && cfg->regs->CCR0_b.RIE) { in uart_ra_sci_b_poll_in()
84 return -EBUSY; in uart_ra_sci_b_poll_in()
87 if (IS_ENABLED(CONFIG_UART_RA_SCI_B_UART_FIFO_ENABLE) ? cfg->regs->FRSR_b.R == 0U in uart_ra_sci_b_poll_in()
88 : cfg->regs->CSR_b.RDRF == 0U) { in uart_ra_sci_b_poll_in()
90 return -1; in uart_ra_sci_b_poll_in()
94 *c = (unsigned char)cfg->regs->RDR; in uart_ra_sci_b_poll_in()
101 const struct uart_ra_sci_b_config *cfg = dev->config; in uart_ra_sci_b_poll_out()
103 while (cfg->regs->CSR_b.TEND == 0U) { in uart_ra_sci_b_poll_out()
106 cfg->regs->TDR_BY = c; in uart_ra_sci_b_poll_out()
111 const struct uart_ra_sci_b_config *cfg = dev->config; in uart_ra_sci_b_err_check()
113 const uint32_t status = cfg->regs->CSR; in uart_ra_sci_b_err_check()
136 fsp_err = R_SCI_B_UART_BaudCalculate(config->baudrate, false, 5000, fsp_baud_setting); in uart_ra_sci_b_apply_config()
139 switch (config->parity) { in uart_ra_sci_b_apply_config()
141 fsp_config->parity = UART_PARITY_OFF; in uart_ra_sci_b_apply_config()
144 fsp_config->parity = UART_PARITY_ODD; in uart_ra_sci_b_apply_config()
147 fsp_config->parity = UART_PARITY_EVEN; in uart_ra_sci_b_apply_config()
150 return -ENOTSUP; in uart_ra_sci_b_apply_config()
152 return -ENOTSUP; in uart_ra_sci_b_apply_config()
154 return -EINVAL; in uart_ra_sci_b_apply_config()
157 switch (config->stop_bits) { in uart_ra_sci_b_apply_config()
159 return -ENOTSUP; in uart_ra_sci_b_apply_config()
161 fsp_config->stop_bits = UART_STOP_BITS_1; in uart_ra_sci_b_apply_config()
164 return -ENOTSUP; in uart_ra_sci_b_apply_config()
166 fsp_config->stop_bits = UART_STOP_BITS_2; in uart_ra_sci_b_apply_config()
169 return -EINVAL; in uart_ra_sci_b_apply_config()
172 switch (config->data_bits) { in uart_ra_sci_b_apply_config()
174 return -ENOTSUP; in uart_ra_sci_b_apply_config()
176 return -ENOTSUP; in uart_ra_sci_b_apply_config()
178 fsp_config->data_bits = UART_DATA_BITS_7; in uart_ra_sci_b_apply_config()
181 fsp_config->data_bits = UART_DATA_BITS_8; in uart_ra_sci_b_apply_config()
184 fsp_config->data_bits = UART_DATA_BITS_9; in uart_ra_sci_b_apply_config()
187 return -EINVAL; in uart_ra_sci_b_apply_config()
190 fsp_config_extend->clock = SCI_B_UART_CLOCK_INT; in uart_ra_sci_b_apply_config()
191 fsp_config_extend->rx_edge_start = SCI_B_UART_START_BIT_FALLING_EDGE; in uart_ra_sci_b_apply_config()
192 fsp_config_extend->noise_cancel = SCI_B_UART_NOISE_CANCELLATION_DISABLE; in uart_ra_sci_b_apply_config()
193 fsp_config_extend->flow_control_pin = UINT16_MAX; in uart_ra_sci_b_apply_config()
195 fsp_config_extend->rx_fifo_trigger = 0x8; in uart_ra_sci_b_apply_config()
198 switch (config->flow_ctrl) { in uart_ra_sci_b_apply_config()
200 fsp_config_extend->flow_control = 0; in uart_ra_sci_b_apply_config()
201 fsp_config_extend->rs485_setting.enable = false; in uart_ra_sci_b_apply_config()
204 fsp_config_extend->flow_control = SCI_B_UART_FLOW_CONTROL_HARDWARE_CTSRTS; in uart_ra_sci_b_apply_config()
205 fsp_config_extend->rs485_setting.enable = false; in uart_ra_sci_b_apply_config()
208 return -ENOTSUP; in uart_ra_sci_b_apply_config()
211 return -ENOTSUP; in uart_ra_sci_b_apply_config()
213 return -EINVAL; in uart_ra_sci_b_apply_config()
225 struct uart_ra_sci_b_data *data = dev->data; in uart_ra_sci_b_configure()
227 err = uart_ra_sci_b_apply_config(cfg, &data->fsp_config, &data->fsp_config_extend, in uart_ra_sci_b_configure()
228 &data->fsp_baud_setting); in uart_ra_sci_b_configure()
233 fsp_err = R_SCI_B_UART_Close(&data->sci); in uart_ra_sci_b_configure()
236 fsp_err = R_SCI_B_UART_Open(&data->sci, &data->fsp_config); in uart_ra_sci_b_configure()
238 memcpy(&data->uart_config, cfg, sizeof(struct uart_config)); in uart_ra_sci_b_configure()
245 struct uart_ra_sci_b_data *data = dev->data; in uart_ra_sci_b_config_get()
247 memcpy(cfg, &data->uart_config, sizeof(*cfg)); in uart_ra_sci_b_config_get()
257 struct uart_ra_sci_b_data *data = dev->data; in uart_ra_sci_b_fifo_fill()
258 const struct uart_ra_sci_b_config *cfg = dev->config; in uart_ra_sci_b_fifo_fill()
261 if (IS_ENABLED(CONFIG_UART_RA_SCI_B_UART_FIFO_ENABLE) && data->sci.fifo_depth > 0) { in uart_ra_sci_b_fifo_fill()
262 while ((size - num_tx > 0) && cfg->regs->FTSR != 0x10U) { in uart_ra_sci_b_fifo_fill()
266 cfg->regs->TDR_BY = tx_data[num_tx++]; in uart_ra_sci_b_fifo_fill()
269 if (size > 0 && cfg->regs->CSR_b.TDRE) { in uart_ra_sci_b_fifo_fill()
273 cfg->regs->TDR_BY = tx_data[num_tx++]; in uart_ra_sci_b_fifo_fill()
282 struct uart_ra_sci_b_data *data = dev->data; in uart_ra_sci_b_fifo_read()
283 const struct uart_ra_sci_b_config *cfg = dev->config; in uart_ra_sci_b_fifo_read()
286 if (IS_ENABLED(CONFIG_UART_RA_SCI_B_UART_FIFO_ENABLE) && data->sci.fifo_depth > 0) { in uart_ra_sci_b_fifo_read()
287 while ((size - num_rx > 0) && cfg->regs->FRSR_b.R > 0U) { in uart_ra_sci_b_fifo_read()
291 rx_data[num_rx++] = cfg->regs->RDR; in uart_ra_sci_b_fifo_read()
293 if (cfg->regs->FRSR_b.R == 0U) { in uart_ra_sci_b_fifo_read()
294 cfg->regs->CFCLR_b.RDRFC = 1U; in uart_ra_sci_b_fifo_read()
295 cfg->regs->FFCLR_b.DRC = 1U; in uart_ra_sci_b_fifo_read()
298 if (size > 0 && cfg->regs->CSR_b.RDRF) { in uart_ra_sci_b_fifo_read()
300 rx_data[num_rx++] = cfg->regs->RDR; in uart_ra_sci_b_fifo_read()
305 cfg->regs->CFCLR_b.ORERC = 0U; in uart_ra_sci_b_fifo_read()
312 const struct uart_ra_sci_b_config *cfg = dev->config; in uart_ra_sci_b_irq_tx_enable()
314 cfg->regs->CCR0 |= (BIT(R_SCI_B0_CCR0_TIE_Pos) | BIT(R_SCI_B0_CCR0_TEIE_Pos)); in uart_ra_sci_b_irq_tx_enable()
319 const struct uart_ra_sci_b_config *cfg = dev->config; in uart_ra_sci_b_irq_tx_disable()
321 cfg->regs->CCR0 &= ~(BIT(R_SCI_B0_CCR0_TIE_Pos) | BIT(R_SCI_B0_CCR0_TEIE_Pos)); in uart_ra_sci_b_irq_tx_disable()
326 struct uart_ra_sci_b_data *data = dev->data; in uart_ra_sci_b_irq_tx_ready()
327 const struct uart_ra_sci_b_config *cfg = dev->config; in uart_ra_sci_b_irq_tx_ready()
329 return (cfg->regs->CCR0_b.TIE == 1U) && in uart_ra_sci_b_irq_tx_ready()
330 (data->csr & (BIT(R_SCI_B0_CSR_TDRE_Pos) | BIT(R_SCI_B0_CSR_TEND_Pos))); in uart_ra_sci_b_irq_tx_ready()
335 struct uart_ra_sci_b_data *data = dev->data; in uart_ra_sci_b_irq_tx_complete()
336 const struct uart_ra_sci_b_config *cfg = dev->config; in uart_ra_sci_b_irq_tx_complete()
338 return (cfg->regs->CCR0_b.TEIE == 1U) && (data->csr & BIT(R_SCI_B0_CSR_TEND_Pos)); in uart_ra_sci_b_irq_tx_complete()
343 const struct uart_ra_sci_b_config *cfg = dev->config; in uart_ra_sci_b_irq_rx_enable()
345 cfg->regs->CCR0_b.RIE = 1U; in uart_ra_sci_b_irq_rx_enable()
350 const struct uart_ra_sci_b_config *cfg = dev->config; in uart_ra_sci_b_irq_rx_disable()
352 cfg->regs->CCR0_b.RIE = 0U; in uart_ra_sci_b_irq_rx_disable()
357 struct uart_ra_sci_b_data *data = dev->data; in uart_ra_sci_b_irq_rx_ready()
358 const struct uart_ra_sci_b_config *cfg = dev->config; in uart_ra_sci_b_irq_rx_ready()
360 return (cfg->regs->CCR0_b.RIE == 1U) && in uart_ra_sci_b_irq_rx_ready()
361 ((data->csr & BIT(R_SCI_B0_CSR_RDRF_Pos)) || in uart_ra_sci_b_irq_rx_ready()
362 (IS_ENABLED(CONFIG_UART_RA_SCI_B_UART_FIFO_ENABLE) && cfg->regs->FRSR_b.DR == 1U)); in uart_ra_sci_b_irq_rx_ready()
367 struct uart_ra_sci_b_data *data = dev->data; in uart_ra_sci_b_irq_err_enable()
369 NVIC_EnableIRQ(data->fsp_config.eri_irq); in uart_ra_sci_b_irq_err_enable()
374 struct uart_ra_sci_b_data *data = dev->data; in uart_ra_sci_b_irq_err_disable()
376 NVIC_DisableIRQ(data->fsp_config.eri_irq); in uart_ra_sci_b_irq_err_disable()
381 const struct uart_ra_sci_b_config *cfg = dev->config; in uart_ra_sci_b_irq_is_pending()
383 const uint32_t ccr0 = cfg->regs->CCR0; in uart_ra_sci_b_irq_is_pending()
384 const uint32_t csr = cfg->regs->CSR; in uart_ra_sci_b_irq_is_pending()
393 cfg->regs->FRSR_b.DR == 1U))); in uart_ra_sci_b_irq_is_pending()
400 struct uart_ra_sci_b_data *data = dev->data; in uart_ra_sci_b_irq_update()
401 const struct uart_ra_sci_b_config *cfg = dev->config; in uart_ra_sci_b_irq_update()
404 data->csr = cfg->regs->CSR; in uart_ra_sci_b_irq_update()
406 if (data->csr & BIT(R_SCI_B0_CSR_PER_Pos)) { in uart_ra_sci_b_irq_update()
409 if (data->csr & BIT(R_SCI_B0_CSR_FER_Pos)) { in uart_ra_sci_b_irq_update()
412 if (data->csr & BIT(R_SCI_B0_CSR_ORER_Pos)) { in uart_ra_sci_b_irq_update()
416 cfg->regs->CFCLR = cfclr; in uart_ra_sci_b_irq_update()
424 struct uart_ra_sci_b_data *data = dev->data; in uart_ra_sci_b_irq_callback_set()
426 data->user_cb = cb; in uart_ra_sci_b_irq_callback_set()
427 data->user_cb_data = cb_data; in uart_ra_sci_b_irq_callback_set()
436 struct uart_ra_sci_b_data *data = dev->data; in async_user_callback()
438 if (data->async_user_cb) { in async_user_callback()
439 data->async_user_cb(dev, event, data->async_user_cb_data); in async_user_callback()
445 struct uart_ra_sci_b_data *data = dev->data; in async_rx_error()
449 .data.rx_stop.data.buf = (uint8_t *)data->rx_buffer, in async_rx_error()
450 .data.rx_stop.data.offset = data->rx_buffer_offset, in async_rx_error()
451 .data.rx_stop.data.len = data->rx_buffer_len, in async_rx_error()
474 struct uart_ra_sci_b_data *data = dev->data; in async_rx_ready()
476 if (data->rx_buffer_len == 0) { in async_rx_ready()
482 .data.rx.buf = (uint8_t *)data->rx_buffer, in async_rx_ready()
483 .data.rx.offset = data->rx_buffer_offset, in async_rx_ready()
484 .data.rx.len = data->rx_buffer_len, in async_rx_ready()
488 data->rx_buffer_offset += data->rx_buffer_len; in async_rx_ready()
489 data->rx_buffer_len = 0; in async_rx_ready()
494 struct uart_ra_sci_b_data *data = dev->data; in async_replace_rx_buffer()
496 if (data->rx_next_buffer != NULL) { in async_replace_rx_buffer()
497 data->rx_buffer = data->rx_next_buffer; in async_replace_rx_buffer()
498 data->rx_buffer_cap = data->rx_next_buffer_cap; in async_replace_rx_buffer()
500 R_SCI_B_UART_Read(&data->sci, data->rx_buffer, data->rx_buffer_cap); in async_replace_rx_buffer()
502 data->rx_next_buffer = NULL; in async_replace_rx_buffer()
503 data->rx_next_buffer_cap = 0; in async_replace_rx_buffer()
512 struct uart_ra_sci_b_data *data = dev->data; in async_release_rx_buffer()
514 if (data->rx_buffer == NULL) { in async_release_rx_buffer()
520 .data.rx.buf = (uint8_t *)data->rx_buffer, in async_release_rx_buffer()
524 data->rx_buffer = NULL; in async_release_rx_buffer()
525 data->rx_buffer_cap = 0; in async_release_rx_buffer()
526 data->rx_buffer_len = 0; in async_release_rx_buffer()
527 data->rx_buffer_offset = 0; in async_release_rx_buffer()
532 struct uart_ra_sci_b_data *data = dev->data; in async_release_rx_next_buffer()
534 if (data->rx_next_buffer == NULL) { in async_release_rx_next_buffer()
540 .data.rx.buf = (uint8_t *)data->rx_next_buffer, in async_release_rx_next_buffer()
544 data->rx_next_buffer = NULL; in async_release_rx_next_buffer()
545 data->rx_next_buffer_cap = 0; in async_release_rx_next_buffer()
550 struct uart_ra_sci_b_data *data = dev->data; in async_update_tx_buffer()
553 .data.tx.buf = (uint8_t *)data->tx_buffer, in async_update_tx_buffer()
554 .data.tx.len = data->tx_buffer_cap, in async_update_tx_buffer()
558 data->tx_buffer = NULL; in async_update_tx_buffer()
559 data->tx_buffer_cap = 0; in async_update_tx_buffer()
564 struct uart_ra_sci_b_data *data = dev->data; in async_tx_abort()
566 if (data->tx_buffer_len < data->tx_buffer_cap) { in async_tx_abort()
569 .data.tx.buf = (uint8_t *)data->tx_buffer, in async_tx_abort()
570 .data.tx.len = data->tx_buffer_len, in async_tx_abort()
575 data->tx_buffer = NULL; in async_tx_abort()
576 data->tx_buffer_cap = 0; in async_tx_abort()
591 return -EINVAL; in fsp_err_to_errno()
593 return -EIO; in fsp_err_to_errno()
595 return -EBUSY; in fsp_err_to_errno()
597 return -ENOTSUP; in fsp_err_to_errno()
601 return -EINVAL; in fsp_err_to_errno()
609 struct uart_ra_sci_b_data *data = dev->data; in uart_ra_sci_b_async_callback_set()
612 data->async_user_cb = cb; in uart_ra_sci_b_async_callback_set()
613 data->async_user_cb_data = cb_data; in uart_ra_sci_b_async_callback_set()
622 struct uart_ra_sci_b_data *data = dev->data; in uart_ra_sci_b_async_tx()
627 if (data->tx_buffer_len < data->tx_buffer_cap) { in uart_ra_sci_b_async_tx()
628 err = -EBUSY; in uart_ra_sci_b_async_tx()
632 err = fsp_err_to_errno(R_SCI_B_UART_Write(&data->sci, buf, len)); in uart_ra_sci_b_async_tx()
637 data->tx_buffer = (uint8_t *)buf; in uart_ra_sci_b_async_tx()
638 data->tx_buffer_cap = len; in uart_ra_sci_b_async_tx()
640 uart_ra_sci_b_async_timer_start(&data->tx_timeout_work, timeout); in uart_ra_sci_b_async_tx()
649 const struct uart_ra_sci_b_config *cfg = dev->config; in disable_tx()
652 cfg->regs->CCR0 &= (uint32_t) ~(R_SCI_B0_CCR0_TIE_Msk | R_SCI_B0_CCR0_TEIE_Msk); in disable_tx()
658 while (cfg->regs->CSR_b.TEND != 1U) { in disable_tx()
661 cfg->regs->CCR0 &= (uint32_t) ~(R_SCI_B0_CCR0_TE_Msk); in disable_tx()
662 while (cfg->regs->CESR_b.TIST != 0U) { in disable_tx()
668 struct uart_ra_sci_b_data *data = dev->data; in uart_ra_sci_b_async_tx_abort()
672 k_work_cancel_delayable(&data->tx_timeout_work); in uart_ra_sci_b_async_tx_abort()
674 if (data->fsp_config.p_transfer_tx) { in uart_ra_sci_b_async_tx_abort()
677 err = fsp_err_to_errno(R_DTC_InfoGet(&data->tx_transfer_ctrl, &transfer_info)); in uart_ra_sci_b_async_tx_abort()
681 data->tx_buffer_len = data->tx_buffer_cap - transfer_info.transfer_length_remaining; in uart_ra_sci_b_async_tx_abort()
683 data->tx_buffer_len = data->tx_buffer_cap - data->sci.tx_src_bytes; in uart_ra_sci_b_async_tx_abort()
686 R_SCI_B_UART_Abort(&data->sci, UART_DIR_TX); in uart_ra_sci_b_async_tx_abort()
699 uart_ra_sci_b_async_tx_abort(data->dev); in uart_ra_sci_b_async_tx_timeout()
705 struct uart_ra_sci_b_data *data = dev->data; in uart_ra_sci_b_async_rx_enable()
706 const struct uart_ra_sci_b_config *cfg = dev->config; in uart_ra_sci_b_async_rx_enable()
709 k_work_cancel_delayable(&data->rx_timeout_work); in uart_ra_sci_b_async_rx_enable()
713 if (data->rx_buffer) { in uart_ra_sci_b_async_rx_enable()
714 err = -EBUSY; in uart_ra_sci_b_async_rx_enable()
718 err = fsp_err_to_errno(R_SCI_B_UART_Read(&data->sci, buf, len)); in uart_ra_sci_b_async_rx_enable()
723 data->rx_timeout = timeout; in uart_ra_sci_b_async_rx_enable()
724 data->rx_buffer = buf; in uart_ra_sci_b_async_rx_enable()
725 data->rx_buffer_cap = len; in uart_ra_sci_b_async_rx_enable()
726 data->rx_buffer_len = 0; in uart_ra_sci_b_async_rx_enable()
727 data->rx_buffer_offset = 0; in uart_ra_sci_b_async_rx_enable()
729 cfg->regs->CCR0_b.RIE = 1U; in uart_ra_sci_b_async_rx_enable()
740 struct uart_ra_sci_b_data *data = dev->data; in uart_ra_sci_b_async_rx_buf_rsp()
742 data->rx_next_buffer = buf; in uart_ra_sci_b_async_rx_buf_rsp()
743 data->rx_next_buffer_cap = len; in uart_ra_sci_b_async_rx_buf_rsp()
750 struct uart_ra_sci_b_data *data = dev->data; in uart_ra_sci_b_async_rx_disable()
751 const struct uart_ra_sci_b_config *cfg = dev->config; in uart_ra_sci_b_async_rx_disable()
756 k_work_cancel_delayable(&data->rx_timeout_work); in uart_ra_sci_b_async_rx_disable()
758 err = fsp_err_to_errno(R_SCI_B_UART_ReadStop(&data->sci, &remaining_byte)); in uart_ra_sci_b_async_rx_disable()
763 if (!data->fsp_config.p_transfer_rx) { in uart_ra_sci_b_async_rx_disable()
764 data->rx_buffer_len = data->rx_buffer_cap - data->rx_buffer_offset - remaining_byte; in uart_ra_sci_b_async_rx_disable()
772 cfg->regs->CFCLR_b.RDRFC = 1U; in uart_ra_sci_b_async_rx_disable()
784 const struct device *dev = data->dev; in uart_ra_sci_b_async_rx_timeout()
788 if (!data->fsp_config.p_transfer_rx) { in uart_ra_sci_b_async_rx_timeout()
789 data->rx_buffer_len = in uart_ra_sci_b_async_rx_timeout()
790 data->rx_buffer_cap - data->rx_buffer_offset - data->sci.rx_dest_bytes; in uart_ra_sci_b_async_rx_timeout()
799 const struct device *dev = fsp_args->p_context; in uart_ra_sci_b_callback_adapter()
800 struct uart_ra_sci_b_data *data = dev->data; in uart_ra_sci_b_callback_adapter()
802 switch (fsp_args->event) { in uart_ra_sci_b_callback_adapter()
804 data->tx_buffer_len = data->tx_buffer_cap; in uart_ra_sci_b_callback_adapter()
809 data->rx_buffer_len = in uart_ra_sci_b_callback_adapter()
810 data->rx_buffer_cap - data->rx_buffer_offset - data->sci.rx_dest_bytes; in uart_ra_sci_b_callback_adapter()
872 const struct uart_ra_sci_b_config *config = dev->config; in uart_ra_sci_b_init()
873 struct uart_ra_sci_b_data *data = dev->data; in uart_ra_sci_b_init()
878 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); in uart_ra_sci_b_init()
884 ret = uart_ra_sci_b_apply_config(&data->uart_config, &data->fsp_config, in uart_ra_sci_b_init()
885 &data->fsp_config_extend, &data->fsp_baud_setting); in uart_ra_sci_b_init()
890 data->fsp_config_extend.p_baud_setting = &data->fsp_baud_setting; in uart_ra_sci_b_init()
891 data->fsp_config.p_extend = &data->fsp_config_extend; in uart_ra_sci_b_init()
894 data->fsp_config.p_callback = uart_ra_sci_b_callback_adapter; in uart_ra_sci_b_init()
895 data->fsp_config.p_context = dev; in uart_ra_sci_b_init()
897 k_work_init_delayable(&data->tx_timeout_work, uart_ra_sci_b_async_tx_timeout); in uart_ra_sci_b_init()
898 k_work_init_delayable(&data->rx_timeout_work, uart_ra_sci_b_async_rx_timeout); in uart_ra_sci_b_init()
901 fsp_err = R_SCI_B_UART_Open(&data->sci, &data->fsp_config); in uart_ra_sci_b_init()
911 struct uart_ra_sci_b_data *data = dev->data; in uart_ra_sci_b_rxi_isr()
914 if (data->user_cb != NULL) { in uart_ra_sci_b_rxi_isr()
915 data->user_cb(dev, data->user_cb_data); in uart_ra_sci_b_rxi_isr()
920 uart_ra_sci_b_async_timer_start(&data->rx_timeout_work, data->rx_timeout); in uart_ra_sci_b_rxi_isr()
922 if (data->fsp_config.p_transfer_rx) { in uart_ra_sci_b_rxi_isr()
924 * The RX DTC is set to TRANSFER_IRQ_EACH, triggering an interrupt for each received in uart_ra_sci_b_rxi_isr()
930 data->rx_buffer_len++; in uart_ra_sci_b_rxi_isr()
931 if (data->rx_buffer_offset + data->rx_buffer_len == data->rx_buffer_cap) { in uart_ra_sci_b_rxi_isr()
934 R_ICU->IELSR_b[data->fsp_config.rxi_irq].IR = 0U; in uart_ra_sci_b_rxi_isr()
940 R_ICU->IELSR_b[data->fsp_config.rxi_irq].IR = 0U; in uart_ra_sci_b_rxi_isr()
947 struct uart_ra_sci_b_data *data = dev->data; in uart_ra_sci_b_txi_isr()
949 if (data->user_cb != NULL) { in uart_ra_sci_b_txi_isr()
950 data->user_cb(dev, data->user_cb_data); in uart_ra_sci_b_txi_isr()
957 R_ICU->IELSR_b[data->fsp_config.txi_irq].IR = 0U; in uart_ra_sci_b_txi_isr()
963 struct uart_ra_sci_b_data *data = dev->data; in uart_ra_sci_b_tei_isr()
966 if (data->user_cb != NULL) { in uart_ra_sci_b_tei_isr()
967 data->user_cb(dev, data->user_cb_data); in uart_ra_sci_b_tei_isr()
972 k_work_cancel_delayable(&data->tx_timeout_work); in uart_ra_sci_b_tei_isr()
975 R_ICU->IELSR_b[data->fsp_config.tei_irq].IR = 0U; in uart_ra_sci_b_tei_isr()
982 struct uart_ra_sci_b_data *data = dev->data; in uart_ra_sci_b_eri_isr()
984 if (data->user_cb != NULL) { in uart_ra_sci_b_eri_isr()
985 data->user_cb(dev, data->user_cb_data); in uart_ra_sci_b_eri_isr()
992 R_ICU->IELSR_b[data->fsp_config.eri_irq].IR = 0U; in uart_ra_sci_b_eri_isr()
1012 R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq)] = \
1014 R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, irq)] = \
1016 R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, irq)] = \
1018 R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), eri, irq)] = \