49 #define REG_MASK(reg) (BIT_MASK(_CONCAT(reg, _LEN)) << _CONCAT(reg, _POS))  macro
220 	reg_val |= (REG_MASK(SEMR_BGDM) | REG_MASK(SEMR_ABCS));  in uart_ra_set_baudrate()
221 	reg_val &= ~(REG_MASK(SEMR_BRME) | REG_MASK(SEMR_ABCSE));  in uart_ra_set_baudrate()
236 	if ((uart_ra_read_8(dev, SCR) & REG_MASK(SCR_RIE))) {  in uart_ra_poll_in()
241 	if ((uart_ra_read_8(dev, SSR) & REG_MASK(SSR_RDRF)) == 0) {  in uart_ra_poll_in()
259 	while (!(uart_ra_read_8(dev, SSR) & REG_MASK(SSR_TEND)) ||  in uart_ra_poll_out()
260 	       !(uart_ra_read_8(dev, SSR) & REG_MASK(SSR_TDRE))) {  in uart_ra_poll_out()
266 	uart_ra_write_8(dev, SCR, reg_val & ~REG_MASK(SCR_TIE));  in uart_ra_poll_out()
269 	while (!(uart_ra_read_8(dev, SSR) & REG_MASK(SSR_TEND)) ||  in uart_ra_poll_out()
270 	       !(uart_ra_read_8(dev, SSR) & REG_MASK(SSR_TDRE))) {  in uart_ra_poll_out()
289 	if (reg_val & REG_MASK(SSR_PER)) {  in uart_ra_err_check()
293 	if (reg_val & REG_MASK(SSR_FER)) {  in uart_ra_err_check()
297 	if (reg_val & REG_MASK(SSR_ORER)) {  in uart_ra_err_check()
301 	reg_val &= ~(REG_MASK(SSR_PER) | REG_MASK(SSR_FER) | REG_MASK(SSR_ORER));  in uart_ra_err_check()
325 	reg_val &= ~(REG_MASK(SCR_TE) | REG_MASK(SCR_RE));  in uart_ra_configure()
330 	reg_val &= ~(REG_MASK(SSR_PER) | REG_MASK(SSR_FER) | REG_MASK(SSR_ORER) |  in uart_ra_configure()
331 		     REG_MASK(SSR_RDRF) | REG_MASK(SSR_TDRE));  in uart_ra_configure()
335 	reg_val &= ~(REG_MASK(LSR_ORER));  in uart_ra_configure()
340 	reg_val &= ~(REG_MASK(SCR_CKE));  in uart_ra_configure()
345 	reg_val &= ~(REG_MASK(SMR_CM) | REG_MASK(SMR_CHR) | REG_MASK(SMR_PE) | REG_MASK(SMR_PM) |  in uart_ra_configure()
346 		     REG_MASK(SMR_STOP) | REG_MASK(SMR_CKS));  in uart_ra_configure()
354 	reg_val |= (REG_MASK(SCR_TE) | REG_MASK(SCR_RE));  in uart_ra_configure()
356 		~(REG_MASK(SCR_TIE) | REG_MASK(SCR_RIE) | REG_MASK(SCR_MPIE) | REG_MASK(SCR_TEIE));  in uart_ra_configure()
438 	reg_val &= ~(REG_MASK(SCR_TIE));  in uart_ra_fifo_fill()
443 	reg_val |= REG_MASK(SCR_TIE);  in uart_ra_fifo_fill()
459 	if ((uart_ra_read_8(dev, SSR) & REG_MASK(SSR_RDRF)) == 0) {  in uart_ra_fifo_read()
481 	reg_val |= (REG_MASK(SCR_TIE));  in uart_ra_irq_tx_enable()
498 	reg_val &= ~(REG_MASK(SCR_TIE));  in uart_ra_irq_tx_disable()
509 	const uint8_t mask = REG_MASK(SSR_TEND) & REG_MASK(SSR_TDRE);  in uart_ra_irq_tx_ready()
523 	reg_val |= REG_MASK(SCR_RIE);  in uart_ra_irq_rx_enable()
540 	reg_val &= ~REG_MASK(SCR_RIE);  in uart_ra_irq_rx_disable()
550 	return !!(uart_ra_read_8(dev, SSR) & REG_MASK(SSR_RDRF));  in uart_ra_irq_rx_ready()
569 	return (uart_ra_irq_rx_ready(dev) && uart_ra_irq_is_enabled(dev, REG_MASK(SCR_RIE))) ||  in uart_ra_irq_is_pending()
570 	       (uart_ra_irq_tx_ready(dev) && uart_ra_irq_is_enabled(dev, REG_MASK(SCR_TIE)));  in uart_ra_irq_is_pending()