Lines Matching refs:UARTE
35 #define UARTE(idx) DT_NODELABEL(uart##idx) macro
36 #define UARTE_HAS_PROP(idx, prop) DT_NODE_HAS_PROP(UARTE(idx), prop)
37 #define UARTE_PROP(idx, prop) DT_PROP(UARTE(idx), prop)
39 #define UARTE_IS_CACHEABLE(idx) DMM_IS_REG_CACHEABLE(DT_PHANDLE(UARTE(idx), memory_regions))
43 NRFX_FOREACH_PRESENT(UARTE, f, sep, off_code, __VA_ARGS__)
115 COND_CODE_1(DT_NODE_HAS_STATUS_OKAY(UARTE(idx)), \
117 DT_NODE_HAS_PROP(UARTE(idx), power_domains)), \
118 (COND_CODE_0(DT_PHA(UARTE(idx), power_domains, id), (1), (0))),\
2371 IRQ_CONNECT(DT_IRQN(UARTE(idx)), DT_IRQ(UARTE(idx), priority), \
2372 isr_handler, DEVICE_DT_GET(UARTE(idx)), 0); \
2373 irq_enable(DT_IRQN(UARTE(idx))); \
2389 #define UARTE_GET_FREQ(idx) DT_PROP(DT_CLOCKS_CTLR(UARTE(idx)), clock_frequency)
2392 COND_CODE_1(DT_CLOCKS_HAS_IDX(UARTE(idx), 0), \
2430 NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP(UARTE(idx)); \
2432 PINCTRL_DT_DEFINE(UARTE(idx)); \
2436 DMM_MEMORY_SECTION(UARTE(idx)); \
2438 DMM_MEMORY_SECTION(UARTE(idx)); \
2440 static uint8_t uarte##idx##_poll_out_byte DMM_MEMORY_SECTION(UARTE(idx));\
2441 static uint8_t uarte##idx##_poll_in_byte DMM_MEMORY_SECTION(UARTE(idx)); \
2455 (IF_ENABLED(DT_CLOCKS_HAS_IDX(UARTE(idx), 0), \
2461 .pcfg = PINCTRL_DT_DEV_CONFIG_GET(UARTE(idx)), \
2464 (.mem_reg = DMM_DEV_TO_REG(UARTE(idx)),)) \
2474 UARTE_DISABLE_RX_INIT(UARTE(idx)), \
2494 PM_DEVICE_DT_DEFINE(UARTE(idx), uarte_nrfx_pm_action, \
2498 DEVICE_DT_DEFINE(UARTE(idx), \
2500 PM_DEVICE_DT_GET(UARTE(idx)), \
2511 BIT_MASK(UARTE##idx##_EASYDMA_MAXCNT_SIZE))] \
2512 DMM_MEMORY_SECTION(UARTE(idx)); \