39 	struct mdma_reg *mdma_reg_base;  member
471 	struct mdma_reg *const mdma_reg_base = config->mdma_reg_base;  in uart_npcx_async_rx_dma_get_status()  local
473 	if (IS_BIT_SET(mdma_reg_base->MDMA_CTL0, NPCX_MDMA_CTL_MDMAEN)) {  in uart_npcx_async_rx_dma_get_status()
474 		*pending_length = mdma_reg_base->MDMA_CTCNT0;  in uart_npcx_async_rx_dma_get_status()
537 	struct mdma_reg *const mdma_reg_base = config->mdma_reg_base;  in uart_npcx_async_tx_dma_get_status()  local
539 	if (IS_BIT_SET(mdma_reg_base->MDMA_CTL1, NPCX_MDMA_CTL_MDMAEN)) {  in uart_npcx_async_tx_dma_get_status()
540 		*pending_length = mdma_reg_base->MDMA_CTCNT1;  in uart_npcx_async_tx_dma_get_status()
554 	struct mdma_reg *const mdma_reg_base = config->mdma_reg_base;  in uart_npcx_async_tx()  local
575 	mdma_reg_base->MDMA_SRCB1 = (uint32_t)buf;  in uart_npcx_async_tx()
576 	mdma_reg_base->MDMA_TCNT1 = len;  in uart_npcx_async_tx()
579 	mdma_reg_base->MDMA_CTL1 |= BIT(NPCX_MDMA_CTL_MDMAEN) | BIT(NPCX_MDMA_CTL_SIEN);  in uart_npcx_async_tx()
596 	struct mdma_reg *const mdma_reg_base = config->mdma_reg_base;  in uart_npcx_async_tx_abort()  local
602 	mdma_reg_base->MDMA_CTL1 &= ~BIT(NPCX_MDMA_CTL_MDMAEN);  in uart_npcx_async_tx_abort()
639 	struct mdma_reg *const mdma_reg_base = config->mdma_reg_base;  in uart_npcx_async_rx_enable()  local
660 	mdma_reg_base->MDMA_DSTB0 = (uint32_t)buf;  in uart_npcx_async_rx_enable()
661 	mdma_reg_base->MDMA_TCNT0 = len;  in uart_npcx_async_rx_enable()
662 	mdma_reg_base->MDMA_CTL0 |= BIT(NPCX_MDMA_CTL_MDMAEN) | BIT(NPCX_MDMA_CTL_SIEN);  in uart_npcx_async_rx_enable()
697 	struct mdma_reg *const mdma_reg_base = config->mdma_reg_base;  in uart_npcx_async_rx_disable()  local
726 	mdma_reg_base->MDMA_CTL0 &= ~BIT(NPCX_MDMA_CTL_MDMAEN);  in uart_npcx_async_rx_disable()
772 	struct mdma_reg *const mdma_reg_base = config->mdma_reg_base;  in uart_npcx_async_dma_load_new_rx_buf()  local
784 	mdma_reg_base->MDMA_DSTB0 = (uint32_t)rx_dma_params->buf;  in uart_npcx_async_dma_load_new_rx_buf()
785 	mdma_reg_base->MDMA_TCNT0 = rx_dma_params->buf_len;  in uart_npcx_async_dma_load_new_rx_buf()
786 	mdma_reg_base->MDMA_CTL0 |= BIT(NPCX_MDMA_CTL_MDMAEN) | BIT(NPCX_MDMA_CTL_SIEN);  in uart_npcx_async_dma_load_new_rx_buf()
845 		struct mdma_reg *const mdma_reg_base = config->mdma_reg_base;  in uart_npcx_isr()  local
860 		if (IS_BIT_SET(mdma_reg_base->MDMA_CTL0, NPCX_MDMA_CTL_TC) &&  in uart_npcx_isr()
861 		    IS_BIT_SET(mdma_reg_base->MDMA_CTL0, NPCX_MDMA_CTL_SIEN)) {  in uart_npcx_isr()
862 			mdma_reg_base->MDMA_CTL0 &= ~BIT(NPCX_MDMA_CTL_SIEN);  in uart_npcx_isr()
864 			mdma_reg_base->MDMA_CTL0 &= ~BIT(NPCX_MDMA_CTL_TC);  in uart_npcx_isr()
871 		if (IS_BIT_SET(mdma_reg_base->MDMA_CTL1, NPCX_MDMA_CTL_TC) &&  in uart_npcx_isr()
872 		    IS_BIT_SET(mdma_reg_base->MDMA_CTL1, NPCX_MDMA_CTL_SIEN)) {  in uart_npcx_isr()
873 			mdma_reg_base->MDMA_CTL1 &= ~BIT(NPCX_MDMA_CTL_SIEN);  in uart_npcx_isr()
875 			mdma_reg_base->MDMA_CTL1 &= ~BIT(NPCX_MDMA_CTL_TC);  in uart_npcx_isr()
1142 			.mdma_reg_base = (struct mdma_reg *)DT_INST_REG_ADDR_BY_IDX(i, 1),         \