170 	return IS_BIT_SET(inst->UFRSTS, NPCX_UFRSTS_RFIFO_NEMPTY_STS);  in uart_npcx_rx_fifo_available()
272 	return IS_BIT_SET(inst->UFTCTL, NPCX_UFTCTL_TEMPTY_EN);  in uart_npcx_irq_tx_is_enabled()
286 	return IS_BIT_SET(inst->UFTSTS, NPCX_UFTSTS_NXMIP);  in uart_npcx_irq_tx_complete()
310 	return IS_BIT_SET(inst->UFRCTL, NPCX_UFRCTL_RNEMPTY_EN);  in uart_npcx_irq_rx_is_enabled()
393 	if (!IS_BIT_SET(inst->UICTRL, NPCX_UICTRL_RBF)) {  in uart_npcx_poll_in()
410 	while (!IS_BIT_SET(inst->UICTRL, NPCX_UICTRL_TBE)) {  in uart_npcx_poll_out()
473 	if (IS_BIT_SET(mdma_reg_base->MDMA_CTL0, NPCX_MDMA_CTL_MDMAEN)) {  in uart_npcx_async_rx_dma_get_status()
539 	if (IS_BIT_SET(mdma_reg_base->MDMA_CTL1, NPCX_MDMA_CTL_MDMAEN)) {  in uart_npcx_async_tx_dma_get_status()
854 		} else if (IS_BIT_SET(inst->UFRCTL, NPCX_UFRCTL_RNEMPTY_EN)) {  in uart_npcx_isr()
860 		if (IS_BIT_SET(mdma_reg_base->MDMA_CTL0, NPCX_MDMA_CTL_TC) &&  in uart_npcx_isr()
861 		    IS_BIT_SET(mdma_reg_base->MDMA_CTL0, NPCX_MDMA_CTL_SIEN)) {  in uart_npcx_isr()
871 		if (IS_BIT_SET(mdma_reg_base->MDMA_CTL1, NPCX_MDMA_CTL_TC) &&  in uart_npcx_isr()
872 		    IS_BIT_SET(mdma_reg_base->MDMA_CTL1, NPCX_MDMA_CTL_SIEN)) {  in uart_npcx_isr()
881 			if (!IS_BIT_SET(inst->UFTSTS, NPCX_UFTSTS_NXMIP)) {  in uart_npcx_isr()
899 	if (IS_BIT_SET(inst->UFTCTL, NPCX_UFTCTL_NXMIP_EN) &&  in uart_npcx_isr()
900 	    IS_BIT_SET(inst->UFTSTS, NPCX_UFTSTS_NXMIP)) {  in uart_npcx_isr()
929 	if (IS_BIT_SET(stat, NPCX_USTAT_DOE)) {  in uart_npcx_err_check()
933 	if (IS_BIT_SET(stat, NPCX_USTAT_PE)) {  in uart_npcx_err_check()
937 	if (IS_BIT_SET(stat, NPCX_USTAT_FE)) {  in uart_npcx_err_check()