16 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart0))
21 	if (!(cfg->uart0->lsr & LPC11U6X_UART0_LSR_RDR)) {  in lpc11u6x_uart0_poll_in()
24 	*c = cfg->uart0->rbr;  in lpc11u6x_uart0_poll_in()
33 	while (!(cfg->uart0->lsr & LPC11U6X_UART0_LSR_THRE)) {  in lpc11u6x_uart0_poll_out()
35 	cfg->uart0->thr = c;  in lpc11u6x_uart0_poll_out()
44 	lsr = cfg->uart0->lsr;  in lpc11u6x_uart0_err_check()
61 static void lpc11u6x_uart0_write_divisor(struct lpc11u6x_uart0_regs *uart0,  in lpc11u6x_uart0_write_divisor()  argument
65 	uart0->lcr |= LPC11U6X_UART0_LCR_DLAB;  in lpc11u6x_uart0_write_divisor()
66 	uart0->dll = div & 0xFF;  in lpc11u6x_uart0_write_divisor()
67 	uart0->dlm = (div >> 8) & 0xFF;  in lpc11u6x_uart0_write_divisor()
68 	uart0->lcr &= ~LPC11U6X_UART0_LCR_DLAB;  in lpc11u6x_uart0_write_divisor()
71 static void lpc11u6x_uart0_write_fdr(struct lpc11u6x_uart0_regs *uart0,  in lpc11u6x_uart0_write_fdr()  argument
74 	uart0->fdr = (div & 0xF) | ((mul & 0xF) << 4);  in lpc11u6x_uart0_write_fdr()
96 	lpc11u6x_uart0_write_divisor(cfg->uart0, dl);  in lpc11u6x_uart0_config_baudrate()
97 	lpc11u6x_uart0_write_fdr(cfg->uart0, div, mul);  in lpc11u6x_uart0_config_baudrate()
171 	dev_cfg->uart0->lcr = flags;  in lpc11u6x_uart0_configure()
205 	while (nr_sent < size && (cfg->uart0->lsr & LPC11U6X_UART0_LSR_THRE)) {  in lpc11u6x_uart0_fifo_fill()
206 		cfg->uart0->thr = data[nr_sent++];  in lpc11u6x_uart0_fifo_fill()
218 	while (nr_rx < size && (cfg->uart0->lsr & LPC11U6X_UART0_LSR_RDR)) {  in lpc11u6x_uart0_fifo_read()
219 		data[nr_rx++] = cfg->uart0->rbr;  in lpc11u6x_uart0_fifo_read()
229 	cfg->uart0->ier = (cfg->uart0->ier & LPC11U6X_UART0_IER_MASK) |  in lpc11u6x_uart0_irq_tx_enable()
242 	cfg->uart0->ier = (cfg->uart0->ier & LPC11U6X_UART0_IER_MASK) &  in lpc11u6x_uart0_irq_tx_disable()
250 	return (cfg->uart0->lsr & LPC11U6X_UART0_LSR_TEMT) != 0;  in lpc11u6x_uart0_irq_tx_complete()
257 	return (cfg->uart0->lsr & LPC11U6X_UART0_LSR_THRE) &&  in lpc11u6x_uart0_irq_tx_ready()
258 		(cfg->uart0->ier & LPC11U6X_UART0_IER_THREINTEN);  in lpc11u6x_uart0_irq_tx_ready()
265 	cfg->uart0->ier = (cfg->uart0->ier & LPC11U6X_UART0_IER_MASK) |  in lpc11u6x_uart0_irq_rx_enable()
273 	cfg->uart0->ier = (cfg->uart0->ier & LPC11U6X_UART0_IER_MASK) &  in lpc11u6x_uart0_irq_rx_disable()
291 	cfg->uart0->ier = (cfg->uart0->ier & LPC11U6X_UART0_IER_MASK) |  in lpc11u6x_uart0_irq_err_enable()
299 	cfg->uart0->ier = (cfg->uart0->ier & LPC11U6X_UART0_IER_MASK) &  in lpc11u6x_uart0_irq_err_disable()
315 	data->cached_iir = cfg->uart0->iir;  in lpc11u6x_uart0_irq_update()
360 	cfg->uart0->lcr |= LPC11U6X_UART0_LCR_WLS_8BITS; /* 8N1 */  in lpc11u6x_uart0_init()
369 	cfg->uart0->fcr = LPC11U6X_UART0_FCR_FIFO_EN;  in lpc11u6x_uart0_init()
381 PINCTRL_DT_DEFINE(DT_NODELABEL(uart0));
383 BUILD_ASSERT(DT_PROP(DT_NODELABEL(uart0), rx_invert) == 0,
385 BUILD_ASSERT(DT_PROP(DT_NODELABEL(uart0), tx_invert) == 0,
389 	.uart0 = (struct lpc11u6x_uart0_regs *)
390 	DT_REG_ADDR(DT_NODELABEL(uart0)),
391 	.clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_NODELABEL(uart0))),
392 	.pincfg = PINCTRL_DT_DEV_CONFIG_GET(DT_NODELABEL(uart0)),
393 	.clkid = DT_PHA_BY_IDX(DT_NODELABEL(uart0), clocks, 0, clkid),
394 	.baudrate = DT_PROP(DT_NODELABEL(uart0), current_speed),
428 DEVICE_DT_DEFINE(DT_NODELABEL(uart0),
438 	IRQ_CONNECT(DT_IRQN(DT_NODELABEL(uart0)),  in lpc11u6x_uart0_isr_config()
439 		    DT_IRQ(DT_NODELABEL(uart0), priority),  in lpc11u6x_uart0_isr_config()
440 		    lpc11u6x_uart0_isr, DEVICE_DT_GET(DT_NODELABEL(uart0)), 0);  in lpc11u6x_uart0_isr_config()
442 	irq_enable(DT_IRQN(DT_NODELABEL(uart0)));  in lpc11u6x_uart0_isr_config()