Lines Matching +full:0 +full:x3
19 #define FDC2X1X_DATA_CH0 0x00
20 #define FDC2X1X_DATA_LSB_CH0 0x01
21 #define FDC2X1X_DATA_CH1 0x02
22 #define FDC2X1X_DATA_LSB_CH1 0x03
23 #define FDC2X1X_DATA_CH2 0x04
24 #define FDC2X1X_DATA_LSB_CH2 0x05
25 #define FDC2X1X_DATA_CH3 0x06
26 #define FDC2X1X_DATA_LSB_CH3 0x07
27 #define FDC2X1X_RCOUNT_CH0 0x08
28 #define FDC2X1X_RCOUNT_CH1 0x09
29 #define FDC2X1X_RCOUNT_CH2 0x0A
30 #define FDC2X1X_RCOUNT_CH3 0x0B
31 #define FDC2X1X_OFFSET_CH0 0x0C
32 #define FDC2X1X_OFFSET_CH1 0x0D
33 #define FDC2X1X_OFFSET_CH2 0x0E
34 #define FDC2X1X_OFFSET_CH3 0x0F
35 #define FDC2X1X_SETTLECOUNT_CH0 0x10
36 #define FDC2X1X_SETTLECOUNT_CH1 0x11
37 #define FDC2X1X_SETTLECOUNT_CH2 0x12
38 #define FDC2X1X_SETTLECOUNT_CH3 0x13
39 #define FDC2X1X_CLOCK_DIVIDERS_CH0 0x14
40 #define FDC2X1X_CLOCK_DIVIDERS_CH1 0x15
41 #define FDC2X1X_CLOCK_DIVIDERS_CH2 0x16
42 #define FDC2X1X_CLOCK_DIVIDERS_CH3 0x17
43 #define FDC2X1X_STATUS 0x18
44 #define FDC2X1X_ERROR_CONFIG 0x19
45 #define FDC2X1X_CONFIG 0x1A
46 #define FDC2X1X_MUX_CONFIG 0x1B
47 #define FDC2X1X_RESET_DEV 0x1C
48 #define FDC2X1X_DRIVE_CURRENT_CH0 0x1E
49 #define FDC2X1X_DRIVE_CURRENT_CH1 0x1F
50 #define FDC2X1X_DRIVE_CURRENT_CH2 0x20
51 #define FDC2X1X_DRIVE_CURRENT_CH3 0x21
52 #define FDC2X1X_MANUFACTURER_ID 0x7E
53 #define FDC2X1X_DEVICE_ID 0x7F
55 #define FDC2X1X_MANUFACTURER_ID_VAL 0x5449
57 #define FDC2X1X_DEVICE_ID_VAL_28BIT 0x3055
58 #define FDC2X1X_DEVICE_ID_VAL 0x3054
60 #define FDC2X1X_READ 0x01u
61 #define FDC2X1X_REG_READ(x) (((x & 0xFF) << 1) | FDC2X1X_READ)
62 #define FDC2X1X_REG_WRITE(x) ((x & 0xFF) << 1)
67 #define FDC2X1X_CLK_DIV_CHX_FIN_SEL_SET(x) (((x) & 0x3) << 12)
68 #define FDC2X1X_CLK_DIV_CHX_FIN_SEL_GET(x) (((x) >> 12) & 0x3)
69 #define FDC2X1X_CLK_DIV_CHX_FREF_DIV_MSK GENMASK(9, 0)
70 #define FDC2X1X_CLK_DIV_CHX_FREF_DIV_SET(x) ((x) & 0x1FF)
71 #define FDC2X1X_CLK_DIV_CHX_FREF_DIV_GET(x) (((x) >> 0) & 0x1FF)
74 #define FDC2X1X_STATUS_ERR_CHAN(x) (((x) >> 14) & 0x3)
75 #define FDC2X1X_STATUS_ERR_WD(x) (((x) >> 11) & 0x1)
76 #define FDC2X1X_STATUS_ERR_AHW(x) (((x) >> 10) & 0x1)
77 #define FDC2X1X_STATUS_ERR_ALW(x) (((x) >> 9) & 0x1)
78 #define FDC2X1X_STATUS_DRDY(x) (((x) >> 6) & 0x1)
79 #define FDC2X1X_STATUS_CH0_UNREADCONV_RDY(x) (((x) >> 3) & 0x1)
80 #define FDC2X1X_STATUS_CH1_UNREADCONV_RDY(x) (((x) >> 2) & 0x1)
81 #define FDC2X1X_STATUS_CH2_UNREADCONV_RDY(x) (((x) >> 1) & 0x1)
82 #define FDC2X1X_STATUS_CH3_UNREADCONV_RDY(x) (((x) >> 0) & 0x1)
86 #define FDC2X1X_ERROR_CONFIG_WD_ERR2OUT_SET(x) (((x) & 0x1) << 13)
87 #define FDC2X1X_ERROR_CONFIG_WD_ERR2OUT_GET(x) (((x) >> 13) & 0x1)
89 #define FDC2X1X_ERROR_CONFIG_AH_WARN2OUT_SET(x) (((x) & 0x1) << 12)
90 #define FDC2X1X_ERROR_CONFIG_AH_WARN2OUT_GET(x) (((x) >> 12) & 0x1)
92 #define FDC2X1X_ERROR_CONFIG_AL_WARN2OUT_SET(x) (((x) & 0x1) << 11)
93 #define FDC2X1X_ERROR_CONFIG_AL_WARN2OUT_GET(x) (((x) >> 11) & 0x1)
95 #define FDC2X1X_ERROR_CONFIG_WD_ERR2INT_SET(x) (((x) & 0x1) << 5)
96 #define FDC2X1X_ERROR_CONFIG_WD_ERR2INT_GET(x) (((x) >> 5) & 0x1)
97 #define FDC2X1X_ERROR_CONFIG_DRDY_2INT_MSK BIT(0)
98 #define FDC2X1X_ERROR_CONFIG_DRDY_2INT_SET(x) (((x) & 0x1) << 0)
99 #define FDC2X1X_ERROR_CONFIG_DRDY_2INT_GET(x) (((x) >> 0) & 0x1)
103 #define FDC2X1X_CFG_ACTIVE_CHAN_SET(x) (((x) & 0x3) << 14)
104 #define FDC2X1X_CFG_ACTIVE_CHAN_GET(x) (((x) >> 14) & 0x3)
106 #define FDC2X1X_CFG_SLEEP_SET_EN_SET(x) (((x) & 0x1) << 13)
107 #define FDC2X1X_CFG_SLEEP_SET_EN_GET(x) (((x) >> 13) & 0x1)
109 #define FDC2X1X_CFG_SENSOR_ACTIVATE_SEL_SET(x) (((x) & 0x1) << 11)
110 #define FDC2X1X_CFG_SENSOR_ACTIVATE_SEL_GET(x) (((x) >> 11) & 0x1)
112 #define FDC2X1X_CFG_REF_CLK_SRC_SET(x) (((x) & 0x1) << 9)
113 #define FDC2X1X_CFG_REF_CLK_SRC_GET(x) (((x) >> 9) & 0x1)
115 #define FDC2X1X_CFG_INTB_DIS_SET(x) (((x) & 0x1) << 7)
116 #define FDC2X1X_CFG_INTB_DIS_GET(x) (((x) >> 7) & 0x1)
118 #define FDC2X1X_CFG_HIGH_CURRENT_DRV_SET(x) (((x) & 0x1) << 6)
119 #define FDC2X1X_CFG_HIGH_CURRENT_DRV_GET(x) (((x) >> 6) & 0x1)
123 #define FDC2X1X_MUX_CFG_AUTOSCAN_EN_SET(x) (((x) & 0x1) << 15)
124 #define FDC2X1X_MUX_CFG_AUTOSCAN_EN_GET(x) (((x) >> 15) & 0x1)
126 #define FDC2X1X_MUX_CFG_RR_SEQUENCE_SET(x) (((x) & 0x3) << 13)
127 #define FDC2X1X_MUX_CFG_RR_SEQUENCE_GET(x) (((x) >> 13) & 0x3)
128 #define FDC2X1X_MUX_CFG_DEGLITCH_MSK GENMASK(2, 0)
129 #define FDC2X1X_MUX_CFG_DEGLITCH_SET(x) ((x) & 0x7)
130 #define FDC2X1X_MUX_CFG_DEGLITCH_GET(x) (((x) >> 0) & 0x7)
134 #define FDC2X1X_RESET_DEV_SET(x) (((x) & 0x1) << 15)
136 #define FDC2X1X_RESET_DEV_OUTPUT_GAIN_SET(x) (((x) & 0x3) << 9)
137 #define FDC2X1X_RESET_DEV_OUTPUT_GAIN_GET(x) (((x) >> 9) & 0x3)
141 #define FDC2X1X_DRV_CURRENT_CHX_IDRIVE_SET(x) (((x) & 0x1F) << 11)
142 #define FDC2X1X_DRV_CURRENT_CHX_IDRIVE_GET(x) (((x) >> 11) & 0x1F)