6  * SPDX-License-Identifier: Apache-2.0
24 	const struct icm42688_dev_cfg *dev_cfg = dev->config;  in icm42688_reset()
26 	/* start up time for register read/write after POR is 1ms and supply ramp time is 3ms */  in icm42688_reset()
29 	/* perform a soft reset to ensure a clean slate, reset bit will auto-clear */  in icm42688_reset()
30 	res = icm42688_spi_single_write(&dev_cfg->spi, REG_DEVICE_CONFIG, BIT_SOFT_RESET);  in icm42688_reset()
33 		LOG_ERR("write REG_SIGNAL_PATH_RESET failed");  in icm42688_reset()
41 	res = icm42688_spi_read(&dev_cfg->spi, REG_INT_STATUS, &value, 1);  in icm42688_reset()
49 		return -EINVAL;  in icm42688_reset()
52 	res = icm42688_spi_read(&dev_cfg->spi, REG_WHO_AM_I, &value, 1);  in icm42688_reset()
59 		return -EINVAL;  in icm42688_reset()
67 	const bool accel_enabled = cfg->accel_pwr_mode != ICM42688_DT_ACCEL_OFF;  in icm42688_compute_fifo_wm()
68 	const bool gyro_enabled = cfg->gyro_pwr_mode != ICM42688_DT_GYRO_OFF;  in icm42688_compute_fifo_wm()
69 	const int pkt_size = cfg->fifo_hires ? 20 : (accel_enabled && gyro_enabled ? 16 : 8);  in icm42688_compute_fifo_wm()
74 	if (cfg->batch_ticks == 0 || (!accel_enabled && !gyro_enabled)) {  in icm42688_compute_fifo_wm()
81 		icm42688_accel_reg_to_hz(cfg->accel_odr, &val);  in icm42688_compute_fifo_wm()
87 		icm42688_gyro_reg_to_odr(cfg->gyro_odr, &val);  in icm42688_compute_fifo_wm()
102 				n1 -= n2;  in icm42688_compute_fifo_wm()
104 				n2 -= n1;  in icm42688_compute_fifo_wm()
113 	modr *= (int64_t)cfg->batch_ticks * pkt_size;  in icm42688_compute_fifo_wm()
123 	struct icm42688_dev_data *dev_data = dev->data;  in icm42688_configure()
124 	const struct icm42688_dev_cfg *dev_cfg = dev->config;  in icm42688_configure()
128 	res = icm42688_spi_single_write(&dev_cfg->spi, REG_INT_SOURCE0, 0);  in icm42688_configure()
131 	if (dev_data->cfg.fifo_en) {  in icm42688_configure()
132 		res = icm42688_spi_single_write(&dev_cfg->spi, REG_FIFO_CONFIG,  in icm42688_configure()
137 			return -EINVAL;  in icm42688_configure()
140 		res = icm42688_spi_single_write(&dev_cfg->spi, REG_SIGNAL_PATH_RESET,  in icm42688_configure()
145 			return -EINVAL;  in icm42688_configure()
152 	uint8_t pwr_mgmt0 = FIELD_PREP(MASK_GYRO_MODE, cfg->gyro_pwr_mode) |  in icm42688_configure()
153 			    FIELD_PREP(MASK_ACCEL_MODE, cfg->accel_pwr_mode) |  in icm42688_configure()
154 			    FIELD_PREP(BIT_TEMP_DIS, cfg->temp_dis);  in icm42688_configure()
157 	res = icm42688_spi_single_write(&dev_cfg->spi, REG_PWR_MGMT0, pwr_mgmt0);  in icm42688_configure()
161 		return -EINVAL;  in icm42688_configure()
169 	uint8_t accel_config0 = FIELD_PREP(MASK_ACCEL_ODR, cfg->accel_odr) |  in icm42688_configure()
170 				FIELD_PREP(MASK_ACCEL_UI_FS_SEL, cfg->accel_fs);  in icm42688_configure()
173 	res = icm42688_spi_single_write(&dev_cfg->spi, REG_ACCEL_CONFIG0, accel_config0);  in icm42688_configure()
176 		return -EINVAL;  in icm42688_configure()
179 	uint8_t gyro_config0 = FIELD_PREP(MASK_GYRO_ODR, cfg->gyro_odr) |  in icm42688_configure()
180 			       FIELD_PREP(MASK_GYRO_UI_FS_SEL, cfg->gyro_fs);  in icm42688_configure()
183 	res = icm42688_spi_single_write(&dev_cfg->spi, REG_GYRO_CONFIG0, gyro_config0);  in icm42688_configure()
186 		return -EINVAL;  in icm42688_configure()
199 	res = icm42688_spi_single_write(&dev_cfg->spi, REG_FIFO_CONFIG, fifo_config_bypass);  in icm42688_configure()
202 		return -EINVAL;  in icm42688_configure()
208 	res = icm42688_spi_single_write(&dev_cfg->spi, REG_FSYNC_CONFIG, 0);  in icm42688_configure()
211 		return -EINVAL;  in icm42688_configure()
213 	res = icm42688_spi_read(&dev_cfg->spi, REG_TMST_CONFIG, &tmst_config, 1);  in icm42688_configure()
216 		return -EINVAL;  in icm42688_configure()
218 	res = icm42688_spi_single_write(&dev_cfg->spi, REG_TMST_CONFIG, tmst_config & ~BIT(1));  in icm42688_configure()
221 		return -EINVAL;  in icm42688_configure()
228 		res = icm42688_spi_single_write(&dev_cfg->spi, REG_INT_CONFIG,  in icm42688_configure()
238 	if ((cfg->accel_odr <= ICM42688_DT_ACCEL_ODR_4000 ||  in icm42688_configure()
239 	     cfg->gyro_odr <= ICM42688_DT_GYRO_ODR_4000)) {  in icm42688_configure()
244 	res = icm42688_spi_single_write(&dev_cfg->spi, REG_INT_CONFIG1, int_config1);  in icm42688_configure()
251 	if (cfg->fifo_en) {  in icm42688_configure()
262 		res = icm42688_spi_single_write(&dev_cfg->spi, REG_FIFO_CONFIG1, fifo_cfg1);  in icm42688_configure()
265 			return -EINVAL;  in icm42688_configure()
268 		/* Set watermark and interrupt handling first */  in icm42688_configure()
273 		res = icm42688_spi_single_write(&dev_cfg->spi, REG_FIFO_CONFIG2, fifo_wml);  in icm42688_configure()
276 			return -EINVAL;  in icm42688_configure()
282 		res = icm42688_spi_single_write(&dev_cfg->spi, REG_FIFO_CONFIG3, fifo_wmh);  in icm42688_configure()
285 			return -EINVAL;  in icm42688_configure()
292 		res = icm42688_spi_single_write(&dev_cfg->spi, REG_FIFO_CONFIG, fifo_config);  in icm42688_configure()
298 		res = icm42688_spi_single_write(&dev_cfg->spi, REG_INT_SOURCE0, int_source0);  in icm42688_configure()
309 		res = icm42688_spi_single_write(&dev_cfg->spi, REG_INT_SOURCE0, int_source0);  in icm42688_configure()
320 	struct icm42688_dev_data *drv_data = dev->data;  in icm42688_safely_configure()
324 		drv_data->cfg = *cfg;  in icm42688_safely_configure()
326 		ret = icm42688_configure(dev, &drv_data->cfg);  in icm42688_safely_configure()
334 	const struct icm42688_dev_cfg *dev_cfg = dev->config;  in icm42688_read_all()
337 	res = icm42688_spi_read(&dev_cfg->spi, REG_TEMP_DATA1, data, 14);  in icm42688_read_all()